초록 ▼

A device for the control of termites is disclosed, wherein the device is a housing which is adapted so that a moisture absorbing attractant in the housing may be heated by the housing being exposed to the natural thermal radiation of the sun when attached to the ground surface. The lower end of the

A device for the control of termites is disclosed, wherein the device is a housing which is adapted so that a moisture absorbing attractant in the housing may be heated by the housing being exposed to the natural thermal radiation of the sun when attached to the ground surface. The lower end of the housing has an opening to the interior for access by termites. Non-toxic and toxic baits may be added to the moisture absorbing attractant when activity is detected or anticipated. The device may be used together with other termite control devices mechanically connected to it. During the day, the device uses the thermal radiation of the sun to heat the attractant which absorbs moisture from the soil. At night, the attractant releases the moisture into the soil, creating a temperature anomaly readily detectable by termites.

대표청구항 ▼

A device for the control of termites is disclosed, wherein the device is a housing which is adapted so that a moisture absorbing attractant in the housing may be heated by the housing being exposed to the natural thermal radiation of the sun when attached to the ground surface. The lower end of the

A device for the control of termites is disclosed, wherein the device is a housing which is adapted so that a moisture absorbing attractant in the housing may be heated by the housing being exposed to the natural thermal radiation of the sun when attached to the ground surface. The lower end of the housing has an opening to the interior for access by termites. Non-toxic and toxic baits may be added to the moisture absorbing attractant when activity is detected or anticipated. The device may be used together with other termite control devices mechanically connected to it. During the day, the device uses the thermal radiation of the sun to heat the attractant which absorbs moisture from the soil. At night, the attractant releases the moisture into the soil, creating a temperature anomaly readily detectable by termites. ell is identical to input signal during a fourth period after the third period, the memory cell has been successfully updated according to the input signal if the data stored in the memory cell is identical to the input signal, and if the data stored in the memory cell is not identical to the input signal, each operation performed during the third and fourth periods is started repeatedly until the data stored in the memory cell is identical to the input signal. 2. The page buffer of claim 1 wherein the flash memory further comprises a detecting circuit for reading the data stored in the memory cell and comparing the input signal with the data stored in the memory cell to determine whether the fourth switch is turned on or not. 3. The page buffer of claim 2 wherein the first switch is turned on during the first period, and the power supply outputs the first voltage to the first terminal of the latch circuit so that the first terminal of the latch circuit approaches a voltage level and the second terminal approaches a second voltage level. 4. The page buffer of claim 3 wherein the first voltage level is the high voltage level, and the second voltage level is the low voltage level. 5. The page buffer of claim 3 wherein when the data stored in the memory cell is different from the input signal, the page buffer will perform a programming operation on the memory cell during the third period to update the data stored in the memory cell by the input signal, and the first switch is turned off and the second switch is turned on so that the power supply outputs the first voltage to the second terminal of the latch circuit for driving the second terminal to approach the first voltage. 6. The page buffer of claim 5 wherein during the third period, the fifth switch is turned on, the power supply outputs the first voltage to drive the second terminal to approach the first voltage, and the fourth switch is turned off. 7. The page buffer of claim 6 wherein during the fourth period, the third switch is turned on, the detecting circuit reads the data stored in the memory cell, and the fourth switch is turned on so that the first terminal of the latch circuit is driven toward the first voltage outputted from the power supply if the data stored in the memory cell is identical to the input signal. 8. The page buffer of claim 7 wherein if the data stored in the memory cell is different from the input signal, each operation performed during the third and fourth periods is started repeatedly until the detecting circuit determines that the data stored in the memory cell is identical to the input signal. 9. The page buffer of claim 3 wherein during the second period, the fourth switch is turned off and the second switch is turned on when the page buffer does not perform a programming operation on the memory cell because the data stored in the memory cell is identical to the input signal. 10. The page buffer of claim 9 wherein the fifth switch is turned on and the power supply outputs the second voltage during the third period. 11. The page buffer of claim 10 wherein during the fourth period, the third switch is turned on and the fourth switch is turned off after the detecting circuit reads the data stored in the memory cell. 12. The page buffer of claim 1 wherein each of the switches is a PMOS transistor. 13. The page buffer of claim 1 wherein each of the switches is an NMOS transistor. 14. The page buffer of claim 1 wherein the latch circuit comprises a plurality of inverters connected between the first and second terminals of the latch circuit. 15. The page buffer of claim 1 wherein each memory cell positioned at the same bit line respectively corresponds to one page buffer. 16. The page buffer of claim 1 wherein the flash memory further comprises a charge pump circuit for generating the first voltage. he method, two adjacent memory cell arrays in memory circuits generally share a row of bit-line sense amplifiers. These sense amplifiers are usually connected to a memory cell array via a number of switches. These switches specifically connect the bit lines of each of two adjacent memory cell arrays to the row of sense amplifiers. By controlling the switches, the row of sense amplifiers can be directed to serve either one of the two adjacent memory cell arrays. The switches may be connected to a bit line select control line. To achieve the desired reduction of power consumption, the present invention controls the bit-line select control line in such a way that the bit-line select control line connected to a currently active memory cell array is switched only when the next memory operation involves an adjacent memory cell array sharing the same row of bit-line sense amplifiers controlled by such bit line select control line. so as to bring about, starting from the origin location, sequential access to further locations addressed by the addressing structure by accessing the two memory banks alternately, by an interleaved method, third circuit means for managing the reading circuits of the two memory banks in accordance with the interleaved method so that two reading processes are executed contemporaneously, but offset in time, in the two memory banks, fourth circuit means for bringing about the selective assignation of the data-transfer structure to the memory bank currently being accessed, in accordance with the interleaved method, and an internal timing structure for controlling the first, second, third and fourth circuit means, the data-transfer structure, and the addressing structure in accordance with second control signals from outside the memory. 2. The memory architecture of claim 1, further comprising fifth circuit means for bringing about completion of the reading in progress and recovery of the last datum read in the storage means upon an external command for disablement of the memory, and for bringing about resumption of the activity of the memory upon the return of the memory from the disablement condition. 3. The memory architecture of claim 2 in which the data-transfer structure comprises a single internal data bus of data-transfer lines, a single register connectible to the internal data bus for the holding storage of the most recent datum read by the reading circuits, means for the selective connection of the internal data bus to the register, and circuits for driving a data bus from outside the memory, the circuits operatively associated with the register and configured to be activated selectively in order to receive the datum read from the register and to transfer it on the data bus outside the memory. 4. The memory architecture of claim 3 in which the fourth circuit means comprise switching means for the selective connection of the lines of the single internal data bus to respective output bus lines of the reading circuits associated with one or with the other of the two memory banks. 5. The memory architecture of claim 4 in which the activation of the driver circuits is controlled by the timing structure. 6. The memory architecture of claim 4 in which the activation of the driver circuits is prevented if the memory is put in "standby" conditions. 7. The memory architecture of claim 6 in which the addressing structure comprises a respective counter for each memory bank. 8. The memory architecture of claim 7 in which the first circuit means comprise means for the selective connection of each of the two counters to lines of an address bus that can carry the address supplied from outside the memory, and an initialization circuit to control the means for the selective connection of the counters to the address bus, the initialization circuit configured to connect the counters to the address bus upon the activation of the first control signal outside the memory. 9. The memory architecture of claim 8 wherein the initialization circuit is configured to perform a filtering of the first control signal outside the memory to prevent undesired loading of spurious addresses into the counters. 10. The memory architecture of claim 9 in which the second circuit means comprise a circuit for generating a pulsed updating signal, for each memory bank a respective circuit for generating a signal for the conditional updating of the respective sequential scanning circuit, and a circuit for controlling the interleaved access to the two memory banks, which circuit generates updating enablement signals that are supplied to the conditional updating signal generators, the control circuit determining the correct sequence of activation of the updating enablement signals on the basis of the address of the origin location. 11. The memory architecture of claim 10 in which the circuit for generating the pulsed updating signal is controlled by the internal t iming structure. 12. The memory architecture of claim 11 in which, after each reading of a memory location of one or of the other memory bank, the timing structure causes the circuit for generating the updating signal to bring about a suspension of the updating signal whilst awaiting an external control signal. 13. The memory architecture of claim 12 in which the control of the circuit for generating the increment signal by the timing structure is independent of but substantially simultaneous with the control of the activation of the driver circuits by the timing structure. 14. The memory architecture of claim 13 in which the timing structure causes the circuit for generating the updating signal to generate the updating signal even when the memory is put in standby after the execution of the last reading. 15. The memory architecture of claim 14 in which the means for the selective connection of the internal data bus to the register are activated upon the control of the increment signal which in turn is turned on after the timing structure has detected an external control signal. 16. The memory architecture of claim 15 in which the circuit for controlling interleaved access operates by detecting the state of a least significant bit of the address of the origin location, which determines the memory bank to which the location to be read firstly belongs and, subsequently, by bringing about access to a sequence of locations belonging alternately to one or to the other of the two memory banks in synchronism with a timing signal generated by the circuit for generating the pulsed updating signal. 17. The memory architecture of claim 16 in which, after the circuit for controlling the interleaved access has determined the memory bank to which the origin location belongs by detecting the state of the least significant bit of the address of the origin location, it is updated autonomously to bring about access to the sequence of locations belonging alternately to one or to the other of the two memory banks, becoming unaffected by the state of the least significant bit of the address present on the address bus. 18. The memory architecture of claim 17 in which the circuit for controlling the interleaved access brings about the assignation of the data-transfer structure to one or to the other of the two memory banks alternately and in accordance with the interleaved access method. 19. The memory architecture of claim 18 in which the addressing structure further comprises, for each memory bank, respective redundancy circuits for the selection of redundancy memory locations in the respective bank in functional replacement of defective locations of the memory bank. 20. A semiconductor memory architecture, comprising: first and second memory banks, each memory bank containing memory locations, selection circuits for selecting the memory locations in the memory bank, and reading circuits for reading data contained in the selected memory locations in each memory bank; a bus configured to transfer data read by the reading circuits from the first and second memory banks to data output terminals; an addressing structure comprising, for each memory bank, a respective circuit for the sequential scanning of the memory locations in each memory bank and operatively connected to the respective circuits for selecting the memory locations in the memory banks; a first circuit for initializing the sequential scanning circuits by an external address and corresponding to an origin location, the first circuit configured to respond to a first external control signal that is indicative of the presence of an address corresponding to the origin location; a second circuit configured to initiate selective updating of the sequential scanning circuits starting from the original location and sequentially accessing further memory locations addressed by the addressing structure by accessing the two memory banks alternatingly by an interleaved method; a third circuit for managing the reading circuits of the two memory banks and according with an interleaved method such that reading of each memory bank is executed contemporaneously but offset in time; a fourth circuit configured to selectively connect the bus to the memory bank currently being read in accordance with the interleaved method; and an internal timing structure for controlling the first, second, third, and fourth circuits, the bus, and the addressing structure in accordance with second external control signals; and a fifth circuit configured to recover the last data read at the completion of reading upon receipt of an external command for disablement, and for resuming reading of the memory upon cessation of the external command for disablement. 21. A semiconductor memory architecture, comprising: first and second memory banks, each memory bank containing memory locations, selection circuits for selecting the memory locations in the memory bank, and reading circuits for reading data contained in the selected memory locations in each memory bank; a bus configured to transfer data read by the reading circuits from the first and second memory banks to data output terminals, wherein the bus comprises a single internal data bus of data-transfer lines, a single register connectible to the internal data bus for storing the most recent data read by the reading circuits, means for selectively connecting the internal data bus to the register, and driving circuits configured to drive external data busses and operatively associated with the register, and configured to be activated selectively in order to receive the data read from the register and to transfer to the external data bus; an addressing structure comprising, for each memory bank, a respective circuit for the sequential scanning of the memory locations in each memory bank and operatively connected to the respective circuits for selecting the memory locations in the memory banks; a first circuit for initializing the sequential scanning circuits by an external address and corresponding to an origin location, the first circuit configured to respond to a first external control signal that is indicative of the presence of an address corresponding to the origin location; a second circuit configured to initiate selective updating of the sequential scanning circuits starting from the original location and sequentially accessing further memory locations addressed by the addressing structure by accessing the two memory banks alternatingly by an interleaved method; a third circuit for managing the reading circuits of the two memory banks and according with an interleaved method such that reading of each memory bank is executed contemporaneously but offset in time; a fourth circuit configured to selectively connect the bus to the memory bank currently being read in accordance with the interleaved method; a fifth circuit configured to recover the last data read at the completion of reading upon receipt of an external command for disablement, and for resuming reading of the memory upon cessation of the external command for disablement; and an internal timing structure for controlling the first, second, third, and fourth a circuits, the bus, and the addressing structure in accordance with second external control signals. 22. A semiconductor memory architecture, comprising: first and second memory banks, each memory bank containing memory locations, selection circuits for selecting the memory locations in the memory bank, and reading circuits for reading data contained in the selected memory locations in each memory bank; a bus configured to transfer data read by the reading circuits from the first and second memory banks to data output terminals, wherein the bus comprises a single internal data bus of data-transfer lines, a single register connectible to the internal data bus for storing the most recent data read by the reading circuits, means for selectively connecting the internal data bus to the register, and driving circuits configured to drive external data busses and operatively associated with the register, and configured to be activated selectively in order to receive the data read from the register and to transfer to the external data bus; an addressing structure comprising, for each memory bank, a respective circuit for the sequential scanning of the memory locations in each memory bank and operatively connected to the respective circuits for selecting the memory locations in the memory banks; a first circuit for initializing the sequential scanning circuits by an external address and corresponding to an origin location, the first circuit configured to respond to a first external control signal that is indicative of the presence of an address corresponding to the origin location; a second circuit configured to initiate selective updating of the sequential scanning circuits starting from the original location and sequentially accessing further memory locations addressed by the addressing structure by accessing the two memory banks alternatingly by an interleaved method; a third circuit for managing the reading circuits of the two memory banks and according with an interleaved method such that reading of each memory bank is executed contemporaneously but offset in time; a fourth circuit configured to selectively connect the bus to the memory bank currently being read in accordance with the interleaved method, wherein the fourth circuit comprises switching means for the selective connection of the lines of the internal data bus to respective output bus lines of the reading circuits associated with each of the two memory banks; a fifth circuit configured to recover the last data read at the completion of reading upon receipt of an external command for disablement, and for resuming reading of the memory upon cessation of the external command for disablement; and an internal timing structure for controlling the first, second, third, and fourth circuits, the bus, and the addressing structure in accordance with second external control signals.