초록 ▼

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array.

대표청구항 ▼

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is onboard the die containing the memory array, but not a cell within the memory array. of memory blocks, if the unit determines that the count of the error correction operation has reached said value. 3. A storage apparatus according to claim 2, wherein said controller unit carries out a recording operation of the count of the error correction operation of the read data in said management area. 4. A storage apparatus according to claim 1, wherein said controller unit keeps count of error occurrence in one operation of the error detection and correction of said read data to determine whether the count of the error occurrence has reached a predetermined value or not and if it determines that the count of the error occurrence has not yet reached the value, the controller unit carries out a recording operation of the data after error correction operation in the same memory block of said plurality of memory blocks. 5. A storage apparatus according to claim 4, wherein said controller unit carries out a recording operation of the data after the error correction operation in a different memory block of said plurality of memory blocks, if the unit determines that the count of the error correction operation has reached said value. 6. A storage apparatus to be coupled with a system bus for receiving a write request accompanied with data through said system bus from a host system comprising: a nonvolatile flash semiconductor memory comprising a plurality of memory blocks and a management area, and a controller unit which is coupled with said system bus and said nonvolatile flash semiconductor memory, and which carries out error detection and correction operations with respect to read data from one of said plurality of memory blocks of said nonvolatile flash semiconductor memory; wherein said controller unit keeps count of error occurrence in one operation of the error detection and correction of the read data to determine whether the count reaches a predetermined value and if it determines that the count of the error occurrence has not yet reached said value, the controller unit carries out a recording operation of data after the error correction operation in the same memory block of said plurality of memory blocks. 7. A storage apparatus according to claim 6, wherein said controller unit carries out a reading operation of the data after the error correction operation in a different memory block of said memory blocks, if the unit determines that the count of the error occurrence has reached said value. 8. A storage apparatus according to claim 7, wherein said value is 3.