초록 ▼

A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and

A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.

대표청구항 ▼

A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and

A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation. ies a boundary of said Ethernet data frame by appending a fixed number of bits to said data frame, irrespective of a size of said Ethernet data frame. 8. The method as claimed in claim 1, wherein said step of encoding at least one Ethernet packet data frame comprises: applying a coding algorithm to said Ethernet packet data frame which identifies a boundary of said Ethernet data frame by appending a fixed number of bits to said data frame, irrespective of a size of said Ethernet data frame. 9. The method as claimed in claim 1, wherein said step of inputting said encoded data frame into said synchronous transmission communications network payload comprises inputting said data frame into at least one virtual container. 10. A method of receiving Ethernet frame based data carried in a synchronous transmission communications network payload comprising the steps of: recovering a stream of encoded Ethernet data frames from said synchronous transmission communications network payload; identifying in said recovered data stream at least one marker designating a boundary of an encoded data frame; and using said marker to recover said Ethernet data frame from said data stream. 11. A method of carrying Ethernet data frames over a synchronous digital hierarchy network, said method comprising the steps of: delineating a plurality of said Ethernet data frames from a received Ethernet data frame bit sequence; encoding each one of said plurality of Ethernet data frames to mark at least one boundary of each of said Ethernet data frames; and incorporating each of said encoded data frames into a synchronous network payload without any intermediate encapsulation of said Ethernet frame based data. 12. A method of adapting Ethernet frame based data for inclusion in a synchronous digital channel, said method comprising the steps of: receiving said Ethernet frame based data over a physical interface; adapting a data rate of said Ethernet frame based data to a rate approximating a synchronous digital data rate of a synchronous network payload; identifying frame boundaries of a plurality of said Ethernet data frames; encoding each one of said plurality of Ethernet data frames with an encoding scheme which designates said frame boundaries; and including said encoded data frames into said synchronous network payload on said synchronous channel without any intermediate encapsulation of said Ethernet frame based data. 13. A method of decoding encoded Ethernet frame based data carried over a synchronous digital channel, said method comprising the steps of: receiving said encoded data frames included in a synchronous network payload of said synchronous digital channel; decoding said encoded data frames to obtain a plurality of markers, each marker designating a boundary of an Ethernet data frame; and using said markers to recover Ethernet frame based data from a synchronous digital bit-stream without any intermediate de-encapsulation of said Ethernet frame based data. 14. Apparatus for incorporating Ethernet frame based data into a synchronous transmission communications network payload without any intermediate encapsulation of said Ethernet frame based data, said apparatus comprising: means for encoding a plurality of Ethernet data frames with a plurality of markers, each marker designating a boundary of one of said plurality of Ethernet data frames; and means for multiplexing encoded data frames into said synchronous transmission communications network payload. 15. A method of encoding Ethernet frame based data into a format suitable for inclusion into a plurality of virtual containers of a synchronous digital network without any intermediate encapsulation of the_Ethernet frame based data, said method comprising the steps of: dividing an Ethernet data frame into a plurality of data blocks, each having a predetermined number of bits; for each said data block, appending an extra bit to said data block, said extra bit designating that said data block comprises said Ethernet data frame; and for a last data block of said Ethernet data frame, appending a second bit, said second bit designating said last data block as an end of said Ethernet data frame. 16. A method as claimed in claim 1, wherein said code identifies the type of payload content within said synchronous network payload. 17. A method as claimed in claim 1, wherein the payload data rate of said plurality of virtually concatenated virtual containers is selected to match as efficiently as possible the data rate of said frame based data. 18. A method as claimed in claim 1, wherein said synchronous network is a synchronous optical network. 19. A method as claimed in claim 1, wherein said synchronous transmission communications network payload comprises at least one virtual container. 20. A method as claimed in claim 1, wherein said synchronous transmission communications network payload comprises a plurality of virtual containers. 21. A method as claimed in claim 1, in which traffic comprising said Ethernet frame based data is mapped to said synchronous network payload at a line rate of said synchronous network payload.