IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0844479
(2001-04-27)
|
발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
32 인용 특허 :
8 |
초록
▼
A component chassis of a server is installed into a rack with a quick-disconnect slide rail. The inner rail member is secured to the component chassis by a quick-connect system having multiple headed protrusions received in corresponding keyhole slots in the rail web, and then slid along the slots u
A component chassis of a server is installed into a rack with a quick-disconnect slide rail. The inner rail member is secured to the component chassis by a quick-connect system having multiple headed protrusions received in corresponding keyhole slots in the rail web, and then slid along the slots until a spring latch snaps into place, without the use of tools. The component chassis, with its attached inner rail members, is then slid into place by inserting the inner rail members in mating outer rail members pre-installed on the rack.
대표청구항
▼
A component chassis of a server is installed into a rack with a quick-disconnect slide rail. The inner rail member is secured to the component chassis by a quick-connect system having multiple headed protrusions received in corresponding keyhole slots in the rail web, and then slid along the slots u
A component chassis of a server is installed into a rack with a quick-disconnect slide rail. The inner rail member is secured to the component chassis by a quick-connect system having multiple headed protrusions received in corresponding keyhole slots in the rail web, and then slid along the slots until a spring latch snaps into place, without the use of tools. The component chassis, with its attached inner rail members, is then slid into place by inserting the inner rail members in mating outer rail members pre-installed on the rack. plurality of integrated circuit devices with one of a bar code reader, an OCR reader, and an optical hole reader. 5. The method of claim 1, wherein at least one assembly step of the series of assembly steps in the manufacturing process includes one of die attach, die cure, wire bond, molding, deflash, lead finish, trim and form, and opens/shorts testing. 6. The method of claim 1, wherein the reading the substantially unique identification code of the mounting substrate of each integrated circuit device of the plurality of integrated circuit devices occurs before the manufacturing process. 7. The method of claim 1, wherein the performing a series of assembly steps in the manufacturing process on the plurality of integrated circuit devices comprises advancing the plurality of integrated circuit devices serially through multiple machines associated with the series of assembly steps. 8. The method of claim 1, wherein the performing a series of assembly steps in the manufacturing process comprises advancing the plurality of integrated circuit devices through parallel machines associated with the series of assembly steps. 9. The method of claim 1, wherein the generating data related to the series of assembly steps of each integrated circuit device of the plurality of integrated circuit devices through the assembly steps comprises generating at least one of assembly equipment data, assembly personnel data, assembly setup data, and time and date data. 10. The method of claim 1, further comprising storing the substantially unique identification code of the mounting substrate of each integrated circuit device of the plurality of integrated circuit devices and wherein the associating the data generated for each integrated circuit device of the plurality of integrated circuit devices with the substantially unique identification code of the mounting substrate of its associated integrated circuit device comprises storing the data generated for each integrated circuit device of the plurality of integrated circuit devices in association with the stored substantially unique identification code of the mounting substrate of its associated integrated circuit device. 11. The method of claim 10, wherein the storing the data generated for each integrated circuit device of the plurality of integrated circuit devices in association with the stored substantially unique identification code of the mounting substrate of its associated integrated circuit device comprises storing the data in a decentralized manner within a computer system so that at least partial access to the stored data may continue during a failure of a centralized portion of the computer system. 12. A manufacturing method comprising: providing a plurality of first substrates in multiple lots; fabricating a plurality of integrated circuit dice on each first substrate of the plurality of first substrates; separating each integrated circuit die of the plurality of integrated circuit dice on each first substrate of the plurality of first substrates, forming one integrated circuit die of a plurality of integrated circuit dice; providing a plurality of mounting substrates, each mounting substrate of the plurality of mounting substrates marked with a substantially unique identification code; providing a front-end identification code associated with each integrated circuit die of the plurality of integrated circuit dice; reading the front-end identification code associated with each integrated circuit die of the plurality of integrated circuit dice; reading the substantially unique identification code marked on each mounting substrate of the plurality of mounting substrates; attaching each integrated circuit die of the plurality of integrated circuit dice to one mounting substrate of the plurality of mounting substrates, forming an integrated circuit device of a plurality of integrated circuit devices; storing the front-end identification code associated with each integrated circuit die of the plurality of integrated circuit dice in each integrated circuit device of the plurality of integrated circuit devices in association with the substantially unique identification code of an associated mounting substrate of the plurality of mounting substrates; performing an assembly step on each integrated circuit device of the plurality of integrated circuit devices including: advancing the plurality of integrated circuit devices through at least one assembly step in a substantially continuous manner; generating data related to the advancement of the plurality of integrated circuit devices through the at least one assembly step; and associating the data generated for each integrated circuit device of the plurality of integrated circuit devices with the substantially unique identification code of an associated mounting substrate of the plurality of mounting substrates so the plurality of integrated circuit devices may be tracked through the assembly step; and back-end testing each integrated circuit device of the plurality of integrated circuit devices. 13. The method of claim 12, further comprising: storing a back-end identification code of each integrated circuit device of the plurality of integrated circuit devices in association with the substantially unique identification code of an associated mounting substrate of the plurality of mounting substrates; and storing back-end testing-related data for each integrated circuit device of the plurality of integrated circuit devices in association with the back-end identification code of each integrated circuit device of the plurality of integrated circuit devices so the plurality of integrated circuit devices may be tracked through the back-end testing. 14. The method of claim 13, wherein storing the back-end identification code of each integrated circuit device of the plurality of integrated circuit devices comprises storing at least one of a fuse ID code and a lot number. 15. The method of claim 13, wherein the front-end identification code and back-end identification code associated with each integrated circuit device of the plurality of integrated circuit devices are identical. 16. The method of claim 12, wherein the providing the plurality of mounting substrates comprises providing substrates selected from a group comprising semiconductor wafers, Silicon-on-Sapphire (SOS) substrates, Silicon-on-Insulator (SOI) substrates, and Silicon-on-Glass (SOG) substrates. 17. The method of claim 12, wherein the fabricating a plurality of integrated circuit dice on each first substrate of the plurality of first substrates comprises fabricating integrated circuit dice selected from a group comprising Dynamic Random Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM) ICs, processor ICs, Application Specific ICs (ASICs), Read Only Memory (ROM) ICs, and Electrically Erasable Programmable ROM (EEPROM) ICs. 18. The method of claim 12, further comprising programming each integrated circuit die of the plurality of integrated circuit dice on each mounting substrate of the plurality of mounting substrates to permanently store a substantially unique fuse ID code, wherein the reading the front-end identification code associated with each integrated circuit die of the plurality of integrated circuit dice comprises reading the substantially unique fuse ID code programmed into each integrated circuit die of the plurality of integrated circuit dice. 19. The method of claim 18, wherein the programming each integrated circuit die of the plurality of integrated circuit dice on each mounting substrate of the plurality of mounting substrates to permanently store the substantially unique fuse ID code comprises programming at least one of fuses and anti-fuses in each integrated circuit die of the plurality of integrated circuit dice on each mounting substrate of the plurality of substrates to permanently store the substantially unique fuse ID cod
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