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Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/315
  • G06F-009/308
출원번호 US-0795672 (2001-02-26)
발명자 / 주소
  • Mirsky, Ethan A.
출원인 / 주소
  • Broadcom Corporation
대리인 / 주소
    Christie, Parker & Hale, LLP
인용정보 피인용 횟수 : 65  인용 특허 : 24

초록

A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path w

대표청구항

A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path w

이 특허에 인용된 특허 (24)

  1. Mohamed Ahmed Hassan, Architecture and method for sharing TLB entries through process IDS.
  2. Deering Michael F. (Mountain View CA), Arithmetic logic system using the output of a first alu to control the operation of a second alu.
  3. Schmidke Waldemar,DEX ; Backhaus Jurgen,DEX ; Liedgens Hans-Peter,DEX ; Pospiech Joachim,DEX, Cheese conveying system.
  4. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  5. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  6. Garverick Tim (Cupertino CA) Camarota Rafael C. (San Jose CA), Dynamic three-state bussing capability in a configurable logic array.
  7. DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
  8. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  9. Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
  10. Miller Bruce E. (Aloha OR) Owen Robert E. (Saratoga CA), High-speed digital multiplier architecture.
  11. Cook Peter W. (Mount Kisco NY), IC chips including ALUs and identical register files whereby a number of ALUs directly and concurrently write results to.
  12. Pierce Kerry M. (Canby OR) Erickson Charles R. (Fremont CA) Huang Chih-Tsung (Burlingame CA) Wieland Douglas P. (Sunnyvale CA), Interconnect architecture for field programmable gate array using variable length conductors.
  13. Mirsky Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
  14. Guyer James M. (Marlboro MA) Epstein David I. (Framingham MA) Keating David L. (Holliston MA) Anderson Walker (Arlington MA) Veres James E. (Framingham MA) Kimmens Harold R. (Hudson MA), Method and apparatus for enhancing the operation of a data processing system.
  15. Leung Wai-Bor (Wescosville PA), Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended fo.
  16. Yetter Jeffry D., Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages.
  17. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  18. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
  19. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  20. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
  21. Saccardi Raymond J. (Laurel MD), Reconfigurable pipelined processor.
  22. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  23. Duong Khue, Tile-based modular routing resources for high density programmable logic device.
  24. Ikenaga Takeshi,JPX ; Ogura Takeshi,JPX, Two-dimensional PE array, content addressable memory, data transfer method and mathematical morphology processing method.

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  1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.
  2. Langhammer, Martin, Angular range reduction in an integrated circuit device.
  3. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  4. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  5. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  6. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.
  7. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.
  8. Langhammer, Martin, Combined floating point adder and subtractor.
  9. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.
  10. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.
  11. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.
  12. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.
  13. Langhammer, Martin, Configuring floating point operations in a programmable device.
  14. Langhammer, Martin, Configuring floating point operations in a programmable logic device.
  15. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.
  16. Dakhil, Dani Y., Dependency checking for reconfigurable logic.
  17. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  18. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  19. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.
  20. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  21. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  22. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.
  23. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.
  24. Deering, Michael F.; Naegle, Nathaniel David; Lavelle, Michael G., Graphics system configured to switch between multiple sample buffer contexts.
  25. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.
  26. Langhammer, Martin, Implementing division in a programmable integrated circuit device.
  27. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.
  28. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.
  29. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.
  30. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  31. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  32. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  33. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  34. Langhammer, Martin, Matrix decomposition in an integrated circuit device.
  35. Kurtz, Brian L., Matrix operations in an integrated circuit device.
  36. Langhammer, Martin, Matrix operations in an integrated circuit device.
  37. Mirsky,Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
  38. Degenaro, Louis R.; Iyengar, Arun K.; Mikalsen, Thomas A.; Rouvellou, Isabelle M., Method and system for caching across multiple contexts.
  39. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.
  40. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  41. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  42. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  43. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
  44. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
  45. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
  46. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  47. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
  48. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
  49. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
  50. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
  51. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
  52. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
  53. Langhammer,Martin, Programmable logic device with routing channels.
  54. Langhammer,Martin, Programmable logic device with routing channels.
  55. Langhammer, Martin, QR decomposition in an integrated circuit device.
  56. Mauer, Volker, QR decomposition in an integrated circuit device.
  57. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
  58. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
  59. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
  60. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  61. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
  62. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
  63. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
  64. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
  65. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
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