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Method to improve the reliability of thermosonic gold to aluminum wire bonds

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/4763
출원번호 US-0949112 (2001-09-07)
발명자 / 주소
  • Smoak, Richard C.
출원인 / 주소
  • Lattice Corporation
대리인 / 주소
    Fliesler Dubb Meyer & Lovejoy, LLP
인용정보 피인용 횟수 : 35  인용 특허 : 6

초록

A method for manufacturing an integrated circuit improves the reliability of thermosonic bonds formed to attach a gold bond wire to an aluminum interconnect pad by reducing corrosion of the aluminum pad regions. In the method, a gold or silver plating is applied to the aluminum bond pads to prevent

대표청구항

A method for manufacturing an integrated circuit improves the reliability of thermosonic bonds formed to attach a gold bond wire to an aluminum interconnect pad by reducing corrosion of the aluminum pad regions. In the method, a gold or silver plating is applied to the aluminum bond pads to prevent

이 특허에 인용된 특허 (6)

  1. Patel Sunil A. ; Chia Chok J. ; Desai Kishor V., Apparatus and method for improving ball joints in semiconductor packages.
  2. Lam Ken (Colorado Springs CO), Bumpless bonding process having multilayer metallization.
  3. Suzuki Masayuki,JPX ; Nishihara Shinji,JPX ; Sahara Masashi,JPX ; Ishida Shinichi,JPX ; Abe Hiromi,JPX ; Tohda Sonoko,JPX ; Uchiyama Hiroyuki,JPX ; Tsugane Hideaki,JPX ; Yoshiura Yoshiaki,JPX, Method for making semiconductor integrated circuit device having interconnection structure using tungsten film.
  4. Hasegawa Hitoshi (Tama JPX), Method for producing a semiconductor device.
  5. Ishii Nobuo (Yamanashi-ken JPX), Plasma processing apparatus.
  6. Havemann Robert H. ; Dixit Girish A. ; Russell Stephen W., Variable doping of metal plugs for enhanced reliability.

이 특허를 인용한 특허 (35)

  1. Tseng, Horng-Huei; Hu, Chenming, Aluminum-based interconnection in bond pad layer.
  2. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  3. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  4. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  7. Yu, Wan-Ling, Method of forming metallic bump and seal for semiconductor device.
  8. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  9. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  10. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  11. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  12. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  13. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  17. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  18. Akiyama, Naoki; Tsuma, Hiroki; Kuno, Takashi; Kanemaru, Toshitaka; Hashimoto, Kenta, Semiconductor device and method of manufacturing the same.
  19. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  20. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  21. Hill, Rodney, System and method for preventing metal corrosion on bond pads.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  33. Nikkhoo, Michael, Ultrasonic bonding.
  34. Chou, Chiu-Ming; Lin, Shih-Hsiung; Lin, Mou-Shiung; Lo, Hsin-Jung, Wire bonding method for preventing polymer cracking.
  35. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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