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Computer system reliability is improved using various techniques to monitor objects (e.g., processes, threads, DLLs, etc.) executing on the system. Such techniques include active techniques, in which information is continually communicated from the object to the monitor, and passive techniques, in w

Computer system reliability is improved using various techniques to monitor objects (e.g., processes, threads, DLLs, etc.) executing on the system. Such techniques include active techniques, in which information is continually communicated from the object to the monitor, and passive techniques, in which the object does not need to repeatedly provide information to the monitor. The monitor determines when an object in the computer system has failed, and initiates appropriate recovery action when such a failure is detected.

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Computer system reliability is improved using various techniques to monitor objects (e.g., processes, threads, DLLs, etc.) executing on the system. Such techniques include active techniques, in which information is continually communicated from the object to the monitor, and passive techniques, in w

Computer system reliability is improved using various techniques to monitor objects (e.g., processes, threads, DLLs, etc.) executing on the system. Such techniques include active techniques, in which information is continually communicated from the object to the monitor, and passive techniques, in which the object does not need to repeatedly provide information to the monitor. The monitor determines when an object in the computer system has failed, and initiates appropriate recovery action when such a failure is detected. n performing the cryptographic operations; storage means coupled to the processor for storing and retrieving information calculated and used in the cryptographic operations; means for securely enclosing said processor, said memory means and said storage means whereby direct access to the cryptographic operations is prevented; a first power source coupled to and supplying power to said processor, said memory means and said storage means, said first power source being external to said secure enclosing means; a second power source coupled to and supplying power to at least said processor, said second power source being internal to said secure enclosing means; and means for switching from said first power source to said second power source when the cryptographic operations are being performed and for switching from said second power source to said first power source when non-cryptographic operations are being performed. 9. The system of claim 8 wherein the second power source is a battery. 10. The system of claim 8 wherein said second power source is a power storage circuit. 11. The system of claim 10 wherein said power storage circuit includes a capacitor, said capacitor being charged during the non-cryptographic operations and being discharged to supply power to at least the processor during the cryptographic operations. 12. The system of claim 8 wherein the cryptographic operations is divided into a plurality segments wherein the second power source is recharged between segments. enerating circuit which receives an external clock for generating internal clocks and is inactivated in response to the power-down signal, a chip select circuit which generates an input enable signal in response to a chip select signal externally supplied and is inactivated in response to the power-down signal, and an input circuit which receives an input signal externally supplied in synchronism with an internal clock. nd a memory controller connected to said host bus, said cache memory and said main memory, wherein said memory controller writes back dirty write back cache data into said main memory in a continuous write back mode when said host bus is not used, wherein said dirty write back cache data is a part of said cache data stored in said cache memory, and each of said dirty write back cache data is written back and each of said dirty write back includes a predetermined portion in said tag address, wherein said memory controller cancels said continuous write back mode when said host bus is used for a memory access to said cache memory or said main memory. 12. A memory system according to claim 11, wherein said memory controller includes: an address decoder connected to said host bus, wherein said address decoder decodes a logical address on said host bus into a physical address and detects that said host bus is used; and a controller cancels said continuous write back mode when it is detected by said address decoder that said host bus is used. 13. A memory system according to claim 12, wherein said predetermined portion is a row address of said physical address in the latest memory access, and said controller issues generation control signals in said continuous write back mode, wherein said memory controller includes: a latch circuit holding said row address; and an address gener