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특허 상세정보

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Forming a conductive structure in a semiconductor device

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-021/336    H01L-021/31    H01L-021/469   
미국특허분류(USC) 438/287; 438/769; 438/787
출원번호 US-0620442 (2000-07-20)
발명자 / 주소
  • Weimer, Ronald A.
  • Hu, Yongjun Jeff
  • Pan, Pai Hung
  • Ratakonda, Deepa
  • Beck, James
  • Thakur, Randhir P. S.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Trop,Pruner&Hu,P.C.
인용정보 피인용 횟수 : 6  인용 특허 : 41
초록
▼

A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layer...

대표
청구항
▼

1. A method of oxidizing layers formed on a base of a semiconductor device, the layers including a first layer containing silicon, the method comprising: generating a predetermined mixture of H2and H2O; providing the mixture to a single-wafer thermal processing chamber; and heating the chamber to selectively oxidize the first layer over one or more other layers. 2. The method of claim 1, further comprising: generating a flow of a mixture containing H2O vapor and H2by injecting an inert gas. 3. The method of claim 2, wherein the inert gas incl...

인용문헌 (41)

  1. Davies John T. (El Sobrante CA) Egbert Stephen J. (Palo Alto CA) Wagar John R. (Bethel Island CA), Apparatus and method for generating steam.
  2. Kikuchi Jun,JPX ; Fujimura Shuzo,JPX ; Iga Masao,JPX, Apparatus for fabricating semiconductor device and method for fabricating semiconductor device.
  3. Ohmi Tadahiro,JPX, Apparatus for forming low-temperature oxide films and method of forming low-temperature oxide films.
  4. Bulucea Constantin ; Kerr Daniel C., Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect tra.
  5. Ronald A. Weimer ; Yongjun Jeff Hu ; Pai Hung Pan ; Deepa Ratakonda ; James Beck ; Randhir P. S. Thakur, Forming a conductive structure in a semiconductor device.
  6. Weimer Ronald A. ; Hu Yongjun Jeff ; Pan Pai Hung ; Ratakonda Deepa ; Beck James ; Thakur Randhir P. S., Forming a conductive structure in a semiconductor device.
  7. Kim Young-sun,KRX ; Lee Nae-in,KRX ; Ko Dae-hong,KRX, Gate electrode for semiconductor device.
  8. Hu Yongjun, Gate electrode stack with diffusion barrier.
  9. Fazan Pierre C. ; Chan Hiang C., Gate having a barrier of titanium silicide.
  10. Prall Kirk D. (Boise ID) Sandhu Gurtej S. (Boise ID) Meikle Scott G. (Boise ID), Low resistance device element and interconnection structure.
  11. Gronet Christian M. ; Knoot Peter A. ; Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Satheesh, Method and apparatus for insitu vapor generation.
  12. Parker Sidney G. (Dallas TX) Wood Jerry (Lewisville TX) Turner Robert T. (Dallas TX) Fischer Craig A. (Plano TX), Method for depositing a Tio2 layer using a periodic and simultaneous tilting and rotating platform motion<.
  13. Suzuki Toshiya (Kawasaki JPX) Ohba Takayuki (Kawasaki JPX) Jinnouchi Shimpei (Tokyo JPX) Murakami Seishi (Tokyo JPX), Method for deposition of a refractory metal nitride and method for formation of a conductive film containing a refractor.
  14. Maiti Bikas ; Paulson Wayne ; Heddleson James, Method for forming a high voltage gate dielectric for use in integrated circuit.
  15. Fujimura Shuzo,JPX ; Kikuchi Jun,JPX, Method for hydrogen plasma down-flow processing and apparatus thereof.
  16. Gronet Christian M. ; Knoot Peter A. ; Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Satheesh, Method for insitu vapor generation for forming an oxide on a substrate.
  17. Nenyei Zsolt,DEX ; Lerch Wilfried,DEX ; Sommer Helmut,DEX, Method for rapid thermal processing (RTP) of silicon substrates.
  18. Horai Masataka (Saga JPX) Adachi Naoshi (Saga JPX) Nishikawa Hideshi (Saga JPX) Sano Masakazu (Saga JPX), Method of annealing a semiconductor wafer in a hydrogen atmosphere to desorb surface contaminants.
  19. Keller David J. (Boise ID), Method of etching WSix films.
  20. Huang Jenn Ming,TWX ; Su Chi-Wen,TWX ; Wu Chung-Cheng,TWX ; Chen Shui-Hung,TWX, Method of forming a metal gate for CMOS devices using a replacement gate process.
  21. Riseman Jacob (Poughkeepsie NY), Method of making integrated circuits using metal silicide contacts.
  22. Lerch Wilfried,DEX ; Roters Georg,DEX ; Muenzinger Peter,DEX ; Mader Roland,DEX, Method of oxidation of semiconductor wafers in a rapid thermal processing (RTP) system.
  23. Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Sathees, Method of oxidizing a substrate in the presence of nitride and oxynitride films.
  24. Hwang Ming ; Hsu Wei-Yung ; Cho Chih-Chen ; Anderson Dirk N., Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing.
  25. Nakao Ken (Sagamihara JPX) Maruchi Sadao (Hachioji JPX) Sakamoto Yoshio (Machida JPX), Oxidation metod.
  26. Hames Greg A., Oxide etch barrier formed by nitridation.
  27. Fujimura Shuzo (Tokyo JPX) Takeuchi Tetsuya (Koube JPX) Miyanaga Takeshi (Ono JPX) Nakano Yoshimasa (Akashi JPX) Matoba Yuji (Koube JPX), Plasma treating method using hydrogen gas.
  28. Bai Gang ; Fraser David B., Polycide film.
  29. Ma Yi ; Merchant Sailesh Mansinh ; Oh Minseok ; Roy Pradip Kumar, Polycide gate structure with intermediate barrier.
  30. Fazan Pierre C. (Boise ID) Figura Thomas A. (Boise ID), Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack.
  31. Homma Kenji,JPX ; Yomiya Koichi,JPX, Processing furnace for oxidizing objects.
  32. Yuuki Tomohiro,JPX, Pyrogenic wet thermal oxidation of semiconductor wafers.
  33. Hwang Ming ; Tsu Robert ; Hsu Wei-Yung, Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication.
  34. Lin Chenyong Frank, Self-aligned storage node definition in a DRAM that exceeds the photolithography limit.
  35. Arima Satoshi,JPX, Semiconductor device with gate electrodes having conductive films.
  36. Dennison Charles H. (Boise ID) Walker Michael A. (Boise ID), Semiconductor processing methods of forming stacked capacitors.
  37. Agnello Paul David ; Cabral ; Jr. Cyril ; Grill Alfred ; Jahnes Christopher Vincent ; Licata Thomas John ; Roy Ronnen Andrew, Tasin oxygen diffusion barrier in multilayer structures.
  38. Ghezzo Mario ; Page Timothy Dietrich ; Gorczyca Thomas Bert ; Bergman Rolf Sverre ; Vakil Himanshu Bachubhai ; Huey Charles Samuel ; Silverstein Seth David, Thermal processor for semiconductor wafers.
  39. Torres Joaquim (Saint Martin le Vinoux FRX) Palleau Jean (Uriage FRX) Bourhila Noureddine (Echirolles FRX), Tungsten silicide self-aligned formation process.
  40. Hasebe Kazuhide (Yamanashi JPX) Takahashi Nobuaki (Hachioji JPX) Sukekawa Keiji (Zama JPX), Vertical heat treatment apparatus.
  41. Inokuchi Yasuhiro,JPX ; Ikeda Fumihide,JPX, Wet-oxidation apparatus and wet-oxidation method.

이 특허를 인용한 특허 (6)

  1. Weimer, Ronald A, Method of composite gate formation.
  2. Weimer,Ronald A, Method of composite gate formation.
  3. Weimer,Ronald A, Method of composite gate formation.
  4. Weimer,Ronald A., Method of composite gate formation.
  5. Bunyk, Paul I, RSFQ Batcher-banyan switching network.
  6. Tam, Norman; Trowbridge, Teresa, RTP process chamber pressure control.

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