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Semiconductor device having a multi-layer pad and manufacturing method thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0976114 (2001-10-15)
우선권정보 JP-0126648 (2001-04-24)
발명자 / 주소
  • Okada, Masakazu
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha
대리인 / 주소
    McDermott, Will & Emery
인용정보 피인용 횟수 : 2  인용 특허 : 24

초록

In the semiconductor device manufactured by the manufacturing method of the present invention, the tungsten layer resistant to an impulsive force is formed without the oxide film layer existing below the second pad. Hence, if an external force is applied to the second pad through an opening upon bon

대표청구항

In the semiconductor device manufactured by the manufacturing method of the present invention, the tungsten layer resistant to an impulsive force is formed without the oxide film layer existing below the second pad. Hence, if an external force is applied to the second pad through an opening upon bon

이 특허에 인용된 특허 (24)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Sardella John C., Integrated circuit with improved pre-metal planarization.
  3. Bajaj Rajeev ; Iyer Subramoney ; Kobayashi Thom ; Saravia Jaime ; Fernandes Mark ; Watts David K., Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects.
  4. Inohara Masahiro,JPX ; Matsuno Tadashi,JPX, Manufacturing method of semiconductor device using chemical mechanical polishing.
  5. Doan Trung Tri ; Lowrey Tyler A., Method for fabricating a flash EEPROM.
  6. Braeckelmann Gregor ; Venkatraman Ramnath ; Herrick Matthew Thomas ; Simpson Cindy R. ; Fiordalice Robert W. ; Denning Dean J. ; Jain Ajay ; Capasso Cristiano, Method for forming a semiconductor device.
  7. Tsui Bing-Yue,TWX, Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits.
  8. Kang Hee Bok,KRX ; Lee Jun Sik,KRX, Method for manufacturing a non-volatile memory device.
  9. Fukao Tetsuhiro,JPX ; Kusumi Yoshihiro,JPX ; Miyatake Hiroshi,JPX ; Fujiwara Nobuo,JPX ; Sakamori Shigenori,JPX ; Iida Satoshi,JPX, Method for manufacturing contact structure.
  10. Hsia Shouli Steve ; Wang Yanhua ; Pallinti Jayanthi, Method for shallow trench isolations with chemical-mechanical polishing.
  11. Kazuyuki Higashi JP; Noriaki Matsunaga JP; Hiroshi Toyoda JP; Akihiro Kajita JP; Tetsuo Matsuda JP; Hisashi Kaneko JP, Method of forming diffusion barrier for copper interconnects.
  12. Hasunuma Masahiko,JPX ; Kaneko Hisashi,JPX, Method of manufacturing an interconnect by dissolving an intermetallic compound film into a main component of a metal film.
  13. Sung-choon Lee KR; Gyung-jin Min KR; Jeong-sic Jeon KR; Kyoung-sub Shin KR, Method of manufacturing semiconductor memory device including various contact studs.
  14. Hsu Wei-Yung ; Hong Qi-Zhong ; Havemann Robert H., Method to improve the texture of aluminum metallization.
  15. Hsing Edward Hsien-Sheng,TWX ; Hong Jen-Der,TWX, Multilevel interconnect structure for integrated circuits.
  16. Kamei Seiji,JPX ; Kurematsu Katsumi,JPX ; Koyama Osamu,JPX, Process for manufacturing interlayer insulating film and display apparatus using this film and its manufacturing method.
  17. Muneyuki Matsumoto JP, Production of semiconductor device.
  18. Bothra Subhas, Reliable interconnect via structures and methods for making the same.
  19. Norio Okada JP, Semiconductor device and method for manufacturing the same.
  20. Li Xiao-Yu ; Mehta Sunil D. ; Pham Van H. ; Marathe Amit P., Semiconductor device having a multi-layer metal interconnect structure.
  21. Lee Sueng-Rok,KRX ; Kim Myung-Sung,KRX ; Lee Yunhee,KRX ; Kim Manjun,KRX, Semiconductor device having multi-layered pad and a manufacturing method thereof.
  22. Higashi Kazuyuki,JPX ; Matsunaga Noriaki,JPX ; Kajita Akihiro,JPX ; Matsuda Tetsuo,JPX ; Iijima Tadashi,JPX ; Kaneko Hisashi,JPX ; Shibata Hideki,JPX ; Nakamura Naofumi,JPX ; Anand Minakshisundaran B, Semiconductor device manufacturing method and semiconductor device.
  23. Ohashi Naofumi,JPX ; Yamaguchi Hizuru,JPX ; Noguchi Junji,JPX ; Owada Nobuo,JPX, Semiconductor integrated circuit device and fabrication process thereof.
  24. Marcyk Gerald T. ; Steigerwald Joseph M., Use of a polish stop layer in the formation of metal structures.

이 특허를 인용한 특허 (2)

  1. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.
  2. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.
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