초록 ▼

A system and method for selectively muting a call of a wireless communication system. A first predetermined signal is received by the wireless communication system. The phone signal has a user signal associated with it. In response to the first predetermined signal, the wireless communication system

A system and method for selectively muting a call of a wireless communication system. A first predetermined signal is received by the wireless communication system. The phone signal has a user signal associated with it. In response to the first predetermined signal, the wireless communication system pauses communication of the user signal to the end user while still maintaining the phone call between the wireless communication system and the conference bridge. In response to a second predetermined signal, the wireless communication system reiates communication of the user signal to the end user.

대표청구항 ▼

A system and method for selectively muting a call of a wireless communication system. A first predetermined signal is received by the wireless communication system. The phone signal has a user signal associated with it. In response to the first predetermined signal, the wireless communication system

A system and method for selectively muting a call of a wireless communication system. A first predetermined signal is received by the wireless communication system. The phone signal has a user signal associated with it. In response to the first predetermined signal, the wireless communication system pauses communication of the user signal to the end user while still maintaining the phone call between the wireless communication system and the conference bridge. In response to a second predetermined signal, the wireless communication system reiates communication of the user signal to the end user. data nodes. 29. The write access operation method in a memory circuit as set forth in claim 28, wherein a feedback control signal generated based on said WL signal activates an access transistor operable to couple said BLE control signal to a second one of said data nodes. 30. The write access operation method in a memory circuit as set forth in claim 29, wherein said BLE control signal is generated at a slower rate than said bitline pair's rate. 31. The write access operation method in a memory circuit as set forth in claim 30, wherein said WL is activated when one of said bitline pair is substantially at near zero potential.