초록 ▼

A lockable media storage box and lock and key combination includes a box having a base and a lid hingedly connected to the base and movable between opened and closed positions. A locking mechanism is movable between locked and unlocked positions to lock and unlock the container. The lock includes lo

A lockable media storage box and lock and key combination includes a box having a base and a lid hingedly connected to the base and movable between opened and closed positions. A locking mechanism is movable between locked and unlocked positions to lock and unlock the container. The lock includes lock pins that slide through aligned lock holes in the base and the lid.

대표청구항 ▼

A lockable media storage box and lock and key combination includes a box having a base and a lid hingedly connected to the base and movable between opened and closed positions. A locking mechanism is movable between locked and unlocked positions to lock and unlock the container. The lock includes lo

A lockable media storage box and lock and key combination includes a box having a base and a lid hingedly connected to the base and movable between opened and closed positions. A locking mechanism is movable between locked and unlocked positions to lock and unlock the container. The lock includes lock pins that slide through aligned lock holes in the base and the lid. pposing substrate have opposite signs having splay alignment formed by parallel alignment process while no voltage is applied, the active matrix liquid crystal display device being subjected to an initialization process for transitioning the splay alignment to bend alignment by application of voltage before liquid crystal display driving and adapted to perform the liquid crystal display driving in the bend alignment, wherein the pixel electrode is provided with a protrusion at a periphery thereof in a plane parallel to a plane defined by an upper surface of said array substrate, and in a region where the protrusion does not overlap with the signal electrode line and the gate electrode line in a vertical direction relative to said plane, and voltage is applied continuously or intermittently applied to the pixel electrode and the common electrode. 2. The active matrix liquid crystal display device according to claim 1, wherein the protrusion is rectangle-shaped. 3. The active matrix liquid crystal display device according to claim 1, wherein the protrusion is triangle-shaped. 4. The active matrix liquid crystal display device according to claim 1, wherein the protrusion is trapezoid-shaped. 5. The active matrix liquid crystal display device according to claim 1, wherein protrusions are formed continuously along the periphery of the pixel electrode. 6. The active matrix liquid crystal display device according to claim 1, wherein at least one of the signal electrode line and the gate electrode line is disposed on the array substrate so as to be provided at position different from position at which the pixel electrode is provided in direction vertical to the array substrate. 7. The active matrix liquid crystal display device according to claim 1, wherein both of the signal electrode line and the gate electrode line are disposed on the array substrate so as to be provided at positions different from position at which the pixel electrode is provided in direction vertical to the array substrate. 8. The active matrix liquid crystal display device according to claim 1, wherein rubbing direction is substantially perpendicular to the signal electrode line. 9. The active matrix liquid crystal display device according to claim 1, wherein rubbing direction is substantially perpendicular to the gate electrode line. 10. The active matrix liquid crystal display device according to claim 1, wherein transversal electric field is generated by the protrusion. 11. The active matrix liquid crystal display device according to claim 10, wherein direction of the transversal electric field is substantially perpendicular to rubbing direction. of forming columnar spacers at a placement density of 100 to 2000/mm2on one of the pair of substrates. 7. A manufacturing method according to claim 6, further comprising the steps of: applying a photosensitive resin on one of said pair of substrates; drying said photosensitive resin to form a photosensitive resin layer; and machining said photosensitive resin layer into columnar spacers by a photo-lithographic method. executed by the output addressing microsequencer for generating addresses to which to store processed image data. 7. The programmable image transform processor of claim 6, wherein the output addressing microsequencer executes the output addressing procedure concurrently with the arithmetic block microsequencer executing the image processing procedure. 8. The programmable image transform processor of claim 6 wherein the programmable addressing block further comprises: a collector having an input buffer for storing data received in response to the generated input address, and also having an output buffer for storing data processed by the arithmetic block. 9. The programmable image transform processor of claim 1 wherein the programmable arithmetic block further comprises: a shift register for receiving requested image data from the programmable addressing block; a coefficient memory for storing coefficients; a multiplier/adder for multiplying the contents of the shift register by the coefficients stored in the coefficient memory; and an accumulator capable of adding consecutive values output by the multiplier/adder, wherein the accumulator outputs the processed image data. 10. The programmable image transform processor of claim 9 wherein the programmable arithmetic block further includes pipeline registers to control the shift register, the multiplier/adder and the accumulator, wherein the arithmetic block microsequencer loads instructions from the arithmetic block memory into one of the pipeline registers to process the image data. 11. The programmable image transform processor of claim 9 further comprising: a histogram memory having bins, each bin having an address, such that the value stored in the accumulator is used as as bin address, and the value stored at the addressed bin is incremented by one. 12. The programmable image transform processor of claim 8 further comprising holding latches for temporarily storing data being transferred from the input buffer to the arithmetic block. 13. A programmable image transform processor for use in a digital image processing system, comprising: a programmable arithmetic block coupled to a memory storing an image processing procedure, the programmable arithmetic block executing the image processing procedure using the image data, wherein the programmable arithmetic block receives digital image data from an image sensor, and the programmable arithmetic block executes the image processing procedure using the digital image data to generate processed digital image data; and a programmable addressing block having an address generator coupled to a microsequencer for generating addresses at which to store the processed digital image data. 14. The programmable image transform processor of claim 13 wherein the programmable addressing block includes: a buffer for storing the processed digital image data from the arithmetic block. 15. A method for processing image data, comprising the steps of: storing an image processing procedure in a memory in an arithmetic block; storing an output addressing procedure in a memory in an addressing block; executing the image processing procedure in the arithmetic block; receiving image data in the arithmetic block from an image sensor; transforming the received image data; outputting the image data to the addressing block to store the processed image data in a memory; and executing the output address procedure in the addressing block, at times overlapping with execution of the image processing procedure by the arithmetic block, so as to generate output addresses at which to store the transformed image data in a memory array. 16. The method of claim 15, further comprising the steps of: accessing a histogram memory using a value of the transformed image data as a histogram address to the histogram memory; and incrementing a histogram value stored at the histogram address, whereby a histogram of the transformed image dat