IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0475647
(1999-12-30)
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발명자
/ 주소 |
- Abbott, Curtis
- Shahri, Homayoun
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출원인 / 주소 |
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대리인 / 주소 |
Blakely, Sokoloff, Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
52 인용 특허 :
1 |
초록
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According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.
대표청구항
▼
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter. cles between asserting a data strobe to the memory bank of the first type and sampling of a data bus, in case of a read operation, and between asserting the data strobe and latching of data into the memory bank, in case of a write operation. 7. The memory interface unit of claim 1, wherein the memory bank to be configured is a memory bank of the second type and an access time is configured as being a multiple of microprocessor clock cycles between asserting a row address strobe and a column address strobe. 8. The memory interface unit of claim 1, for further coupling the microprocessor to an input/output device of a directly addressable memory-mapped input/output type. 9. The memory interface unit of claim 1, wherein a global bus strobe is asserted which acts as a data strobe for a memory bank of the first type and which acts as a column address strobe for a memory bank of the second type. 10. A computer system, comprising: a processor, coupled to a memory interface; a first memory bank with program code stored therein, the first memory bank coupled to the memory interface to receive at least a first chip select signal; a second memory bank coupled to the memory interface to receive at least a second chip select input signal; wherein the memory interface is adapted to, at a first time period, receive a first address and responsive thereto generate the first chip select signal, and receive a second address and responsive thereto generate the second chip select input signal; and further adapted to, at a second time period, the second time period being subsequent to a transfer of the program code from the first memory bank to the second memory bank, receive the first address and generate the second chip select input signal. 11. The computer system of claim 10, wherein the first memory bank comprises non-volatile memory. 12. The computer system of claim 11, further comprising a direct memory access (DMA) controller coupled to the memory interface. 13. The computer system of claim 12, wherein the second memory bank comprises static random access memory (SRAM). 14. The computer system of claim 12, wherein the second memory bank comprises dynamic random access memory (DRAM). 15. A method of operating a computer system, comprising: resetting a processor; performing a first programming of a plurality of configuration registers in a memory interface, the configuration registers adapted to provide control information for the operation of the memory interface; transferring data stored in a first memory bank having a first base address, to a second memory bank having a second base address, the first base address being different from the second base address; and performing, subsequent to transferring the data from the first memory bank to the second memory bank, a second programming of the plurality of configuration registers such that the second memory bank is accessed at addresses using the first base address; wherein the data transferred from the first memory bank to the second memory bank represents instructions to be executed by the processor. 16. The method of claim 15, further comprising: selecting, at the memory interface, one of an address received from the processor, and an address received from a DMA controller. 17. The method of claim 16, further comprising: accessing and executing instructions from the second memory bank. 18. The method of claim 16, wherein the first memory bank comprises a non-volatile memory having first access characteristics, and the second memory bank comprises a volatile memory having second access characteristics. 19. The method of claim 18, wherein the first and second access characteristics are such that instructions in the second memory bank can be accessed in less time than instructions in the first memory bank.
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