[특허]Method of producing a semiconductor layer on a substrate

Method of producing a semiconductor layer on a substrate 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/46
출원번호	US-0032335 (2001-12-19)
우선권정보	EP-0870312 (2000-12-21)
발명자 / 주소	Poortmans, Jef Flamand, Giovanni Bilyalov, Renat
출원인 / 주소	Interuniversitair Microelektronica Centrum (IMEC), Umicore
대리인 / 주소	Knobbe, Martens, Olson & Bear LLP
인용정보	피인용 횟수 : 37 인용 특허 : 11

초록 ▼

A method of producing a semiconductor layer onto a semiconductor substrate. The method comprises providing a first semiconductor substrate, and providing a second semiconductor substrate. The method also comprises producing a porous layer, which has a porosity profile, on top of the first semiconductor substrate, and producing a porous layer, which has a porosity profile, on top of the second semiconductor substrate. The method further comprises bringing the porous layer of the second substrate into contact with the porous layer of the first substrate, so as to form a bond between the two substrates, performing a thermal annealing step, and lifting off of the second substrate, leaving a layer of the second substrate's semiconductor material attached to the first substrate.

대표청구항 ▼

1. A method of producing a semiconductor layer onto a semiconductor substrate, comprising the steps of: producing a first porous layer on top of a first semiconductor substrate, said first porous layer having a first porosity profile; producing a second porous layer on top of a second semiconductor substrate, said second porous layer having a second porosity profile; bringing said second porous layer into contact with said first porous layer, so as to form a bond between said first and second substrates; performing a thermal annealing step; and lifting off said second substrate, leaving a layer of material of said second substrate attached to said first substrate. 2. The method according to claim 1, wherein said second porosity profile is formed by a first layer of high porosity adjacent to the surface of said second substrate, followed by a second layer of lower porosity and a third layer of higher porosity. 3. The method according to claim 1, wherein said first porosity profile is formed by a first layer of high porosity adjacent to the surface of said first substrate, followed by a second layer of lower porosity. 4. The method according to claim 1, wherein a layer of the material of said second substrate is formed on top of said first substrate, said layer of the material of said second substrate comprising a number of voids. 5. The method according to claim 1, wherein said first substrate comprises a Si-substrate and said second substrate comprises a Ge-substrate. 6. The method according to claim 1, wherein said first substrate comprises a Si-substrate and said second substrate comprises a GaAs substrate. 7. The method according to claim 1, wherein each of said first and said second substrates comprises Si substrates. 8. The method according to claim 1, wherein said step of producing the first and second porous layers comprises anodization. 9. The method according to claim 8, further comprising the steps of: forming a porous layer on said second substrate through anodization in a solution of HF and acetic acid; and bringing said first substrate into contact with said second substrate while said second substrate is still in the solution and during said anodization. 10. The method according to claim 8, further comprising the steps of: forming a porous layer on said second substrate through anodization in a solution of HF and acetic acid; removing said second substrate from said solution; and bringing said first substrate into contact with said second substrate. 11. A semiconductor device produced in accordance with the method of claim 10. 12. The device according to claim 11, wherein said device comprises an opto-electronic device.

이 특허에 인용된 특허 (11)

Luryi Sergey (Millington NJ), Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrat.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Method of producing a semiconductor layer on a substrate 원문보기

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이 특허에 인용된 특허 (11)

이 특허를 인용한 특허 (37)

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Method of producing a semiconductor layer on a substrate 원문보기

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연구과제 타임라인

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이 특허에 인용된 특허 (11)

이 특허를 인용한 특허 (37)

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