초록

An ergonomic and proprioceptive handle design for instruments is disclosed. The handle can be used with a wide variety of medical instruments, such as a rongeur, as well as other instruments, such as guns and staplers.

대표청구항 ▼

An ergonomic and proprioceptive handle design for instruments is disclosed. The handle can be used with a wide variety of medical instruments, such as a rongeur, as well as other instruments, such as guns and staplers. ng: a BIST maintenance interface for communicating test data to the CAM core.

An ergonomic and proprioceptive handle design for instruments is disclosed. The handle can be used with a wide variety of medical instruments, such as a rongeur, as well as other instruments, such as guns and staplers. ng: a BIST maintenance interface for communicating test data to the CAM core. 5. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising: a search port for enabling searches of the CAM core; a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; and a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search. 6. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, wherein the search port includes multiplexer logic for selecting between BIST search data and functional search data. 7. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, wherein the maintenance port includes multiplexer logic for selecting: (a) between BIST row and block addresses and functional mode row and block addresses; and (b) between BIST write data and functional mode write data. 8. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, further comprising an IEEE 1149.1 controller for communicating control signals to and from the BIST controller. 9. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, wherein BIST circuit enables BIST searches on every clock cycle, the searches performed on every cycle enabling at-speed BIST testing. 10. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, further comprising: a search port comparator; a search port interface; a maintenance port comparator; and a maintenance port interface; wherein the search port interface, the maintenance port interface, the search port comparator, and the maintenance port comparator are each distributed and have expansion capabilities, which limits a number of global wires required to communicate read/write and search data and results. 11. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core as recited in claim 1, wherein the BIST testing only tests one row per cycle and the BIST testing is separate from a priority encoder (PE) BIST testing. 12. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising: a search port for enabling searches of the CAM core; a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search; and a search port interface that receives only 1 bit of test data from the BIST controller, other bits being generated internally to the search port interface, so as to limit a number of required global wires. 13. A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising: a search port for enabling searches of the CAM core; a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core; a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selecte