초록 ▼

The present invention provides a method for solving the Navier-Stokes equation of viscous, incompressible laminar flows with moving free surfaces in complex domains. The method uses fixed mesh control volume-finite element techniques to track the flow. A gauss point velocity vector is defined as the

The present invention provides a method for solving the Navier-Stokes equation of viscous, incompressible laminar flows with moving free surfaces in complex domains. The method uses fixed mesh control volume-finite element techniques to track the flow. A gauss point velocity vector is defined as the average of its nodal counterpart, such that the gauss point velocity vector is constant over the element. The gauss point velocity vector is then inserted into the continuity constraint to form the Poisson pressure equation for solving the pressure field. The solution to the Poisson pressure equation is unique, the common checker-board problem is therefore eliminated. The corrected pressure field is substituted into the momentum equations, so that the resulting velocity field satisfies the continuity equation. Since velocity and pressure are evaluated at the same order, the global mass conservation can be evaluated to machine round-off tolerances.

대표청구항 ▼

The present invention provides a method for solving the Navier-Stokes equation of viscous, incompressible laminar flows with moving free surfaces in complex domains. The method uses fixed mesh control volume-finite element techniques to track the flow. A gauss point velocity vector is defined as the

The present invention provides a method for solving the Navier-Stokes equation of viscous, incompressible laminar flows with moving free surfaces in complex domains. The method uses fixed mesh control volume-finite element techniques to track the flow. A gauss point velocity vector is defined as the average of its nodal counterpart, such that the gauss point velocity vector is constant over the element. The gauss point velocity vector is then inserted into the continuity constraint to form the Poisson pressure equation for solving the pressure field. The solution to the Poisson pressure equation is unique, the common checker-board problem is therefore eliminated. The corrected pressure field is substituted into the momentum equations, so that the resulting velocity field satisfies the continuity equation. Since velocity and pressure are evaluated at the same order, the global mass conservation can be evaluated to machine round-off tolerances. he radio receiver of claim 1, wherein said pair of input transistors are NMOS type transistors which have normal threshold voltages of greater than 1 V. 7. The radio receiver of claim 1, wherein said pair of input transistors are PMOS type transistors which have normal threshold voltages of less than negative 1 V. 8. A radio frequency mixer circuit comprising: a pair of transmission gates, each comprising a pair of MOSFET transistors, respective local oscillator signals being supplied to gates of the transistors, and an input signal being supplied to inputs of the transmission gates, wherein the transistors of the transmission gates have reduced thresholds. 9. A radio frequency mixer circuit as claimed in claim 8, wherein the local oscillator signals are supplied through a pair of local oscillator drivers to the transmission gates, each local oscillator driver is formed from a pair of transistors, wherein the transistors of the local oscillator drivers have normal thresholds. 10. The radio frequency mixer circuit of claim 9, wherein said pair of transmission gates and said pair of local oscillator drivers are formed into a single monolithic integrated chip. 11. The radio frequency mixer circuit of claim 9, wherein said pair of transmission gates are PMOS type transistors which have reduced threshold voltages of less than 0.5 V. 12. The radio frequency mixer circuit of claim 9, wherein said pair of local oscillator drivers are PMOS type transistors which have normal threshold voltages of greater than 1 V. 13. The radio frequency mixer circuit of claim 9, wherein said pair of transmission gates are NMOS type transistors which have reduced threshold voltages of greater than negative 0.5 V. 14. The radio frequency mixer circuit of claim 9, wherein said pair of local oscillator drivers are NMOS type transistors which have normal threshold voltages of less than negative 1 V. 15. A radio frequency mixer circuit comprising: an in-phase mixer which comprises, first and second transistors wherein a source of the first and second transistors are connected to each other and a drain of the first and second transistors are connected to each other; and a quadrature mixer which comprises, third and fourth transistors wherein a source of the third and fourth transistors are connected to each other and a drain of the first and second transistors are connected to each other, wherein the gates of the third and fourth transistors are supplied with local oscillator signals through a first local oscillator driver, and wherein the gates of the third and fourth transistors are supplied with local oscillator signals through a second local oscillator driver, the first and second local oscillator drivers each comprising a pair of common gate transistors, wherein the first, second, third and forth transistors have reduced threshold voltages and the transistors of the local oscillator driver have normal threshold voltages. 16. A radio receiver circuit comprising: an amplifier stage comprising, a first input transistor, wherein a drain of the first input transistor is connected to ground, a fourth input transistor, wherein a source of the fourth input transistor is connected to a supply voltage, wherein a gate of the first transistor is connected to a gate of the fourth transistor, wherein an input frequency signal is supplied to the gate of the first input transistor and supplied inverted to the gate of the fourth input transistor, and wherein the first and the fourth input transistors are normal threshold transistors, a second transistor, wherein a gate of the second transistor is connected to the supply voltage divided by two, and a third transistor, wherein a gate of the third transistor is connected to the supply voltage divided by two inverted, wherein a source of the third transistor is connected to a drain of the fourth transistor, wherein a source of the second transistor is connected to a drain of the third transistor, whe