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Self-organizing hardware processing entities that cooperate to execute requests

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/08
출원번호 US-0560928 (2000-04-30)
발명자 / 주소
  • McAllister, Curtis R.
  • Douglas, Robert C.
출원인 / 주소
  • Hewlett-Packard Development Company, L.P.
인용정보 피인용 횟수 : 35  인용 특허 : 10

초록

A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions a

대표청구항

A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions a

이 특허에 인용된 특허 (10)

  1. Mann Eytan,ILX, Apparatus for maintaining an ordered list.
  2. Weber Karl (Altdorf DEX) Spichtinger Klaus (Stulln DEX) Kremer Karl-Theo (Adelsdorf DEX), Bus controller and electronic device in a system in which several electronic devices are networked.
  3. Wolff James J., Dynamic load balancing of a network of client and server computers.
  4. Iacobovici Sorin ; Bryg William R. ; Hassoun Joseph H., Forming linked lists using content addressable memory.
  5. Kevin Michael Jordan ; Kun-Lung Wu ; Philip Shi-Lung Yu, Load balancing cooperating cache servers by shifting forwarded request.
  6. Lau Joseph C. ; Roy Subhash C. ; Callaerts Dirk L. M.,BEX ; Vandeweerd Ivo Edmond Nicole,BEX, Method and apparatus for allocation and management of shared memory with data in memory stored as multiple linked lists.
  7. Miskowiec Norman L., Method and apparatus for balancing processing requests among a plurality of servers based on measurable characteristics.
  8. Stamm Rebecca L. (Wellesley MA) Bahar Ruth I. (Lincoln NE) Wade Nicholas D. (Folsom CA), Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills.
  9. Klausmeier Daniel E. ; Sathe Satish P., System for buffering data in the network having a linked list for each of said plurality of queues.
  10. Konopik Bradly J. (Gaithersburg MD) Bradley David J. (Boca Raton FL) Reed Martin A. (Rockville MD) Tannenbaum Alan R. (Washington Grove MD) Turner Michael R. (Boca Raton FL), System for managing a plurality of shared interrupt handlers in a linked-list data structure.

이 특허를 인용한 특허 (35)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  6. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  7. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  8. Blake,Michael A.; German,Steven M.; Mak,Pak kin; Seigler,Adrian E.; Van Huben,Gary A., Bus protocol for a switchless distributed shared memory computer system.
  9. Blake,Michael A.; Mak,Pak kin; Seigler,Adrian E.; VanHuben,Gary A., Coherency management for a "switchless" distributed shared memory computer system.
  10. Blake,Michael A.; Mak,Pak kin; Seigler,Adrian E.; VanHuben,Gary A., Coherency management for a "switchless" distributed shared memory computer system.
  11. Heller, Jr., Thomas J., Computing system with guest code support of transactional memory.
  12. Baum, Richard I.; Heller, Jr., Thomas J., Computing system with optimized support for transactional memory.
  13. Heller, Jr., Thomas J., Computing system with transactional memory using millicode assists.
  14. Heller, Jr., Thomas J., Computing system with transactional memory using millicode assists.
  15. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  16. Van Doren,Stephen R., Generalized active inheritance consistency mechanism having linked writes.
  17. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  18. Blankenship, Robert G., Implied directory state updates.
  19. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  20. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  21. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  22. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  23. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  24. Strader, Todd A.; Rider, Scot H., Multi-source dual-port linked list purger.
  25. Tsien,Benjamin, Ring interconnect with multiple coherence networks.
  26. Rowlands,Joseph B.; Hayter,Mark D., Source triggered transaction blocking.
  27. Vartti,Kelvin S.; Weber,Ross M., System and method for handling memory requests in a multiprocessor shared memory system.
  28. Motta,Frank, System for hardware assisted free list management.
  29. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  30. Heller, Jr., Thomas J; Baum, Richard L, Transactional memory computing system with support for chained transactions.
  31. Heller, Jr., Thomas J.; Le, Hung Qui, Transactional memory system which employs thread assists using address history tables.
  32. Heller, Jr., Thomas J., Transactional memory system with efficient cache support.
  33. Heller, Jr., Thomas J., Transactional memory system with efficient cache support.
  34. Heller, Jr., Thomas J., Transactional memory system with efficient cache support.
  35. Heller, Jr., Thomas J., Transactional memory system with fast processing of common conflicts.
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