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Microprocessor architecture capable of supporting multiple heterogeneous processors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
  • G06F-013/36
출원번호 US-0884943 (2001-06-21)
발명자 / 주소
  • Lentz, Derek J.
  • Hagiwara, Yasuaki
  • Lau, Te-Li
  • Tang, Cheng-Long
  • Nguyen, Le Trong
출원인 / 주소
  • Seiko Epson Corporation
대리인 / 주소
    Sterne, Kessler, Goldstein & Fox P.L.L.C.
인용정보 피인용 횟수 : 44  인용 특허 : 22

초록 ▼

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor

대표청구항 ▼

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor

이 특허에 인용된 특허 (22)

  1. Joyce Thomas F. (Westford MA) Miller Robert C. (Braintree MA) Vogt Marc C. (Nashua NH), Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data.
    상세보기
  2. Lockwood James M. (West Columbia SC) Cochcroft ; Jr. Arthur F. (Lexington SC), Arbiter circuit and method.
    상세보기
  3. Buch Bruce D. (Westborough MA) MacGregor Cecil D. (Milford MA), Arbiter with programmable dynamic request prioritization.
    상세보기
  4. Ludemann James J. (Mountain View CA) Bechtolsheim Andreas (Stanford CA), Arbitrator for allocating access to data processing resources.
    상세보기
  5. Bosshart Patrick W. (Dallas TX), Cache memory addressable by both physical and virtual addresses.
    상세보기
  6. Yamamoto Akio (Hadano JPX) Kubo Kanji (Hadano JPX), Cache storage apparatus.
    상세보기
  7. Bowater Ronald J. (Romsey NY GB2) Larky Steven P. (New York NY) St. Clair Joe C. (Round Rock TX) Sidoli Paolo G. (Romsey GB2), Flexible dynamic memory controller.
    상세보기
  8. Coyle Richard W. (Dunstable MA) Chao Zenja (North Andover MA) Berg Thomas B. (West Lafayette IN), I/O bus to system interface.
    상세보기
  9. Jackson Daniel K. (Portland OR), Interface between a microprocessor chip and peripheral subsystems.
    상세보기
  10. Ogata Yukihiko (Kawasaki JPX), Memory controller including a priority order determination circuit.
    상세보기
  11. Yoshida Kenichi (Tokyo JPX), Memory controller which can carry out a high speed access when supplied with input addresses with a time interval left b.
    상세보기
  12. Webb ; Jr. David A. (Berlin MA) Hetherington Ricky C. (Northboro MA) Murray John E. (Acton MA) Fossum Tryggve (Northboro MA) Manley Dwight P. (Holliston MA), Method and apparatus for ordering and queueing multiple memory requests.
    상세보기
  13. Iijima Yasuo (Yokohama JPX), Microcomputer incorporating memory.
    상세보기
  14. Lentz Derek J. (Los Gatos CA) Hagiwara Yasuaki (Santa Clara CA) Lau Te-Li (Palo Alto CA) Tang Cheng-Long (San Jose CA) Nguyen Le Trong (Monte Sereno CA), Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU.
    상세보기
  15. Schwartz Martin J. (Worcester MA) Becker Robert D. (Shirley MA), Multi-processor system with cache memories.
    상세보기
  16. Gove Robert J. (Plano TX) Guttag Karl M. (Missouri City TX) Balmer Keith (Bedfordshire GB2) Ing-Simmons Nicholas K. (Bedfordshire GB2), Multi-processor with crossbar link of processors and memories and method of operation.
    상세보기
  17. Uehara Izushi (Tokyo JPX), Priority selector.
    상세보기
  18. Mote ; Jr. L. Randall (Laguna Hills CA), Queue management mechanism which allows entries to be processed in any order.
    상세보기
  19. Beard Douglas R. (Eleva WI) Phelps Andrew E. (Eau Claire WI) Woodmansee Michael A. (Eau Claire WI) Blewett Richard G. (Altoona WI) Lohman Jeffrey A. (Eau Claire WI) Silbey Alexander A. (Eau Claire WI, Scalar/vector processor.
    상세보기
  20. Dshkhunian Valery L. (K-482 ; korpus 338A ; kv. 73 Moscow SUX) Ivanov Eduard E. (14 Parkovaya ulitsa ; 16 ; kv. 6 Moscow SUX) Kovalenko Sergei S. (k-498 ; korpus 421 ; kv. 3 Moscow SUX) Mashevich Pav, Single-chip microcomputer.
    상세보기
  21. Okura Hiroyuki (Hadano JPX) Imamura Jiro (Hiratsuka JPX) Yamamoto Norio (Isehara JPX) Watanabe Masaya (Hadano JPX), Storage control apparatus.
    상세보기
  22. Balmer Keith (6 Salcombe Close Bedford (Bedfordshire) GB2 MK40 38A) Ing-Simmons Nicholas K. (74 Lincroft ; Oakley Bedford (Bedfordshire) TX GB2 MK43 7SS) Guttag Karl M. (4015 S. Sandy Ct. Missouri Ci, Switch matrix having integrated crosspoint logic and method of operation.
    상세보기

이 특허를 인용한 특허 (44)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
    상세보기
  3. Ansari, Ahmad R.; Applebaum, Jeffery H.; Shenoy, Kunal R., Arbitration for an embedded processor block core in an integrated circuit.
    상세보기
  4. Milner, Marius C., Automatic proxy setting modification.
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  5. Milner, Marius C., Automatic proxy setting modification.
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  6. Wallach, Steven J.; Brewer, Tony, Compiler for generating an executable comprising instructions for a plurality of different instruction sets.
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  7. Abhay,Gupta; Hellwig,Frank; K철nig,Dietmar; Tuck,Richard, Configuration and method having a first device and a second device connected to the first device through a cross bar.
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  8. Wallach, Steven J.; Brewer, Tony, Dispatch mechanism for dispatching instructions from a host processor to a co-processor.
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  9. Brewer, Tony; Wallach, Steven J., Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor.
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  10. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
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  11. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  12. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
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  13. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  14. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
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  15. Goren, Ori; Netanel, Yaron, Interconnect and a method for designing an interconnect.
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  16. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
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  17. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.
    상세보기
  18. Scheuermann, W. James, Method and system for reconfigurable channel coding.
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  19. Neuman, Darren, Method of analyzing non-preemptive DRAM transactions in real-time unified memory architectures.
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  20. Neuman, Darren, Method of analyzing non-preemptive DRAM transactions in real-time unified memory architectures.
    상세보기
  21. Lentz, Derek J.; Hagiwara, Yasuaki; Lau, Te-Li; Tang, Cheng-Long; Nguyen, Le Trong, Microprocessor architecture capable of supporting multiple heterogeneous processors.
    상세보기
  22. Wallach, Steven J.; Brewer, Tony, Microprocessor architecture having alternative memory access paths.
    상세보기
  23. Wallach, Steven J.; Brewer, Tony, Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set.
    상세보기
  24. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
    상세보기
  25. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
    상세보기
  26. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
    상세보기
  27. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.
    상세보기
  28. Fredricksen, Eric Russell; Feng, Hanping; Kataru, Naga Sridhar; Harik, Georges, Prioritized preloading of documents to client.
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  29. Lemonovich, John E.; Sharp, William A., Programmable logic apparatus employing shared memory, vital processor and non-vital communications processor, and system including the same.
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  30. Garg, Sanjiv; Lentz, Derek J.; Nguyen, Le Trong; Chen, Sho Long, RISC microprocessor architecture implementing multiple typed register sets.
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  31. Fredricksen, Eric Russell; Feng, Hanping; Kataru, Naga Sridhar; Harik, Georges, Refreshing cached documents and storing differential document content.
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  32. Kethareswaran, Harendran; Rao, Amit, Resource arbiter.
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  33. Garg, Sanjiv; Iadonato, Kevin Ray; Nguyen, Le Trong; Wang, Johannes, Superscalar RISC instruction scheduling.
    상세보기
  34. Neuman,Darren, System and method for arbitrating clients in a hierarchical real-time DRAM system.
    상세보기
  35. Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for handling exceptions and branch mispredictions in a superscalar microprocessor.
    상세보기
  36. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
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  37. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.
    상세보기
  38. Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.
    상세보기
  39. Fredricksen, Eric Russell; Schneider, Fritz John; Dean, Jeffrey Adgate; Ghemawat, Sanjay; Provos, Niels; Harik, Georges, System and method of accessing a document efficiently through multi-tier web caching.
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  40. Sharp, William A.; Lemonovich, John E.; Werner, James C.; Ding, Zhu; Weber, Lawrence A., System and method to serially transmit vital data from two processors.
    상세보기
  41. Date,Atsushi, System controller using plural CPU's.
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  42. Eriksen, Bjorn Marius Aamodt; Rennie, Jeffrey Glenn; Laraki, Othman, Systems and methods for client authentication.
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  43. Eriksen, Bjorn Marius Aamodt; Rennie, Jeffrey Glen; Laraki, Othman, Systems and methods for client cache awareness.
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  44. Brewer, Tony, Systems and methods for mapping a neighborhood of data to general registers of a processing element.
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