IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0620007
(2000-07-20)
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발명자
/ 주소 |
- Peterson, Tom
- Diaz, Jorge Andres Diaz
- Cucci, Gerald R.
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출원인 / 주소 |
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대리인 / 주소 |
Patterson, Thuente, Skaar & Christensen, P.A.
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인용정보 |
피인용 횟수 :
17 인용 특허 :
64 |
초록
▼
A sensor operable at temperatures in excess of 400° C. is described. The sensor of the present invention operates without fluid fill, is non-porous, non-contaminating, and has no exterior exposed metallic components. The sensor includes a non-porous, impermeable sensing diaphragm that may be positio
A sensor operable at temperatures in excess of 400° C. is described. The sensor of the present invention operates without fluid fill, is non-porous, non-contaminating, and has no exterior exposed metallic components. The sensor includes a non-porous, impermeable sensing diaphragm that may be positioned in direct contact with fluids in an ultra-pure environment. The non-porous surface may be comprised of a layer of single crystal sapphire that is glassed to a backing plate. The sensor of the present invention is suitable for use in a chemically inert pressure transducer module for sensing pressures and/or temperatures in process fluids and may be molded directly into the high temperature plastic housing of the pressure transducer module.
대표청구항
▼
A sensor operable at temperatures in excess of 400° C. is described. The sensor of the present invention operates without fluid fill, is non-porous, non-contaminating, and has no exterior exposed metallic components. The sensor includes a non-porous, impermeable sensing diaphragm that may be positio
A sensor operable at temperatures in excess of 400° C. is described. The sensor of the present invention operates without fluid fill, is non-porous, non-contaminating, and has no exterior exposed metallic components. The sensor includes a non-porous, impermeable sensing diaphragm that may be positioned in direct contact with fluids in an ultra-pure environment. The non-porous surface may be comprised of a layer of single crystal sapphire that is glassed to a backing plate. The sensor of the present invention is suitable for use in a chemically inert pressure transducer module for sensing pressures and/or temperatures in process fluids and may be molded directly into the high temperature plastic housing of the pressure transducer module. when the fourth and fifth layers are in registration. 12. The method of claim 11, wherein said fourth and fifth patterns are comprised of multiple, separated segments, each side of the other combined pattern having at least one segment and one discontinuity associated respectively with said fourth and fifth patterns. 13. A method for simultaneously measuring registration relative to each other of more than two layers of a semiconductor wafer, comprising: forming at least first, second and third layers which overlay each other; providing a first pattern in a designated location of said first layer; providing a second pattern in a designated location of said second layer, said second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location; providing a third pattern in a designated location of said third layer, said third pattern having said given shape and said given size of said second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of said second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other; and simultaneously measuring an overlay registration error between said first pattern and each of said second and third patterns. 14. A method for simultaneously measuring registration relative to each other of more than two layers of a semiconductor wafer being fabricated with a stepper controlled to position a plurality of stepper fields to apply each layer of the wafer, comprising: providing a first pattern in a designated location of a stepper field forming a first layer; providing a second pattern in a designated location of a stepper field forming a second layer, said second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location; providing a third pattern in a designated location of a stepper field forming a third layer, said third pattern having said given shape and said given size of said second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of said second and third patterns fits within at least one discontinuity in the other when the second and third layers are in registration with each other; and simultaneously measuring an overlay registration error between said first pattern and each of said second and third patterns. 15. A method for fabricating a semiconductor wafer, comprising: forming at least first, second and third layers which overlay each other; providing a first pattern in a designated location of said first layer; providing a second pattern in a designated location of said second layer, said second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location; providing a third pattern in a designated location of said third layer, said third pattern having said given shape and said given size of said second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of said second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other; measuring a first overlay registration error between said first pattern and said second pattern, and simultaneously measuring a second overlay registration error between said first pattern and said third pattern; obtaining an average error of said first and second overlay registration measurement errors; and automatically determining further processing of said wafer based on said average error. 16. The method of claim 15, wherein said average error is a weighted average. 17. The method of claim 16, wherein weighting for said weighted average is based on acceptable tolerances for the first and second overlay registration errors. 18. The method of claim 15, wherein said automatic determination of further processing includes a pass/fail for said wafer. 19. The method of claim 15, wherein said automatic determination of further processing includes adjusting the stepper to correct for first and second overlay registration measurement errors. 20. A method for fabricating a semiconductor wafer, comprising: forming at least first, second and third layers which overlay each other; providing a first pattern in a designated location of said first layer; providing a second pattern in a designated location of said second layer, said second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location; providing a third pattern in a designated location of said third layer, said third pattern having said given shape and said given size of said second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of said second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other; measuring a first overlay registration error between said first pattern and said second pattern; measuring a second overlay registration error between said first pattern and said third pattern; obtaining an average error of said first and second overlay registration measurement errors; and automatically determining further processing of said wafer based on said average error, wherein said automatic determination of further processing includes a pass/fail for said wafer.
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