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Microelectronic device package with conductive elements and associated method of manufacture 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
출원번호 US-0927302 (2001-08-10)
발명자 / 주소
  • Eldridge, Jerome M.
  • Farrar, Paul A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Perkins Coie LLP
인용정보 피인용 횟수 : 84  인용 특허 : 58

초록

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an ext

대표청구항

A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an ext

이 특허에 인용된 특허 (58)

  1. Grant Larry A. (Saratoga CA) Marder James M. (Shaker Heights OH) Wright Wayne L. (San Jose CA), Aluminum-beryllium alloys having high stiffness and low thermal expansion for memory devices.
  2. Corisis David ; Moden Walter, Chip package.
  3. Corisis David J., Chip scale package with heat spreader and method of manufacture.
  4. Bertolet Allan ; Fiore James ; Gramatski Eberhard, Consolidated chip design for wire bond and flip-chip package technologies.
  5. Wensel Richard W., Encapsulated integrated circuit packaging.
  6. Kermani Ahmad (Fremont CA) Johnsgard Kristian E. (San Jose CA) Galewski Carl (Berkeley CA), Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure.
  7. Akram Salman ; Kinsman Larry, Heat sink chip package and method of making.
  8. Polese Frank J. ; Ocheretyansky Vladimir, Heat-dissipating package for microcircuit devices and process for manufacture.
  9. Corisis David J., IC package with dual heat spreaders.
  10. Corisis David J. ; Reynolds Tracy ; Slaughter Michael ; Cram Daniel ; Nevill Leland R. ; King Jerrold L., Integrated circuit package alignment feature.
  11. Bothra Subhas ; Qian Ling Q., Integrated circuit structure having an air dielectric and dielectric support pillars.
  12. Zhao Bin, Interconnect structure and method employing air gaps between metal lines and between metal layers.
  13. Havemann Robert H. ; Jeng Shin-Puu ; Gnade Bruce E. ; Cho Chih-Chen, Interconnect structure with an integrated low density dielectric.
  14. Aaron Schoenfeld ; Jerry M. Brooks, Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die.
  15. Jeng Shin-Puu, Low capacitance interconnect structure for integrated circuits.
  16. Wollesen Donald L., Low capacitance interconnection.
  17. Buynoski Matthew S., Low dielectric semiconductor device with rigid lined interconnection system.
  18. Fjelstad Joseph, Low profile socket for microelectronic components and method for making the same.
  19. Fjelstad Joseph, Low profile socket for microelectronic components and method for making the same.
  20. Petefish William George, Method and apparatus for improving wireability in chip modules.
  21. DiStefano Thomas H. ; Fjelstad Joseph, Method for fabricating microelectronic assemblies.
  22. Loboda Mark Jon, Method for forming air bridges.
  23. Schoenfeld Aaron ; Brooks Jerry M., Method for supporting an integrated circuit die.
  24. Smith John W. ; Fjelstad Joseph, Method of assembling a semiconductor chip package.
  25. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Method of forming a semiconductor structure having an air region.
  26. Farrar Paul A., Method of forming a support structure for air bridge wiring of an integrated circuit.
  27. Farrar Paul A., Method of forming foamed polymeric material for an integrated circuit.
  28. Soclof Sidney I. (San Gabriel CA), Method of forming integrated circuit chip transmission line.
  29. Gnade Bruce E. (Dallas TX) Cho Chih-Chen (Richardson TX) Smith Douglas M. (Albuquerque NM), Method of making a semiconductor device using a low dielectric constant material.
  30. Corisis David J., Method of making chip scale package with heat spreade.
  31. Te Velde, Ties S., Method of manufacturing a wiring system.
  32. Fujihira Mitsuaki (Yokohama JPX), Method of manufacturing semiconductor device.
  33. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  34. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  35. Kenneth A. Peterson ; Robert D. Watson, Microelectronic device package with an integral window.
  36. Kevin S. Petrarca ; Rebecca D. Mih, Microprocessor having air as a dielectric and encapsulated lines.
  37. Bhansali Ameet ; Zhu Qing, Multi-layer C4 flip-chip substrate.
  38. Kinsman Larry D., Multilayered lead frame for semiconductor package.
  39. Akram Salman ; Wark James M., Packaged die on PCB with heat sink encapsulant.
  40. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  41. Zaidel Simon A. (Manlius NY) Alcorn Terrence S. (Liverpool NY) Kopp William F. (Liverpool NY) Pifer George C. (North Syracuse NY), Process for making air bridges for integrated circuits.
  42. White Lawrence H. (Vestal NY), Process for surface mounting flip chip carrier modules.
  43. Koopman Nicholas G. (Raleigh NC) Rinne Glenn A. (Cary NC) Turlik Iwona (Raleigh NC), Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bump.
  44. Allen Timothy J., Removable heat sink bumpers on a quad flat package.
  45. Lawrence A. Clevenger ; Louis Lu-Chen Hsu, Semi-sacrificial diamond for air dielectric formation.
  46. Nishimoto Shozo (Tokyo JPX), Semiconductor memory device.
  47. Akram Salman, Semiconductor package having interlocking heat sinks and method of fabrication.
  48. Kinsman Larry D., Semiconductor package having metal foil die mounting plate.
  49. Moden Walter, Semiconductor package having stacked dice and leadframes and method of fabrication.
  50. Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
  51. Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
  52. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Semiconductor structure having an air region and method of forming the semiconductor structure.
  53. Ornstein Leonard (White Plains NY), Specimen mounting adhesive composition.
  54. Andoh Takeshi (Tokyo JPX), Static semiconductor memory device.
  55. Nishida Seiki,JPX ; Nakashima Junji,JPX ; Serikawa Osami,JPX ; Ochiai Ikuo,JPX, Steel wire of high strength excellent in fatigue characteristics.
  56. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  57. Jiang Tongbi ; Johnson Mark S., Thermally enhanced semiconductor package.
  58. Kinsman Larry D. ; Brooks Jerry M., Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages.

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  1. Franosch, Martin; Meckes, Andreas; Nessler, Winfried; Oppermann, Klaus-Gunter, Apparatus for housing a micromechanical structure.
  2. Franosch,Martin; Meckes,Andreas; Nessler,Winfried; Oppermann,Klaus Gunter, Apparatus for housing a micromechanical structure and method for producing the same.
  3. Johnson, Mark S., Conductive structures for microfeature devices and methods for fabricating microfeature devices.
  4. Johnson, Mark S., Conductive structures for microfeature devices and methods for fabricating microfeature devices.
  5. Johnson, Mark S., Conductive structures for microfeature devices and methods for fabricating microfeature devices.
  6. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  7. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  8. Clyne, Craig T.; Fernandez, John C., Die attached to a support member by a plurality of adhesive members.
  9. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  10. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  11. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  12. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  13. Farrar,Paul A.; Forbes,Leonard; Ahn,Kie Y.; Geusic,Joseph E.; Bhattacharyya,Arup; Reinberg,Alan R., Integrated circuit cooling and insulating device and method.
  14. Farrar,Paul A., Integrated circuit cooling system and method.
  15. Farrar,Paul A., Integrated circuit cooling system and method.
  16. Jiang, Tongbi, Method and apparatus for attaching microelectronic substrates and support members.
  17. Jiang,Tongbi, Method and apparatus for attaching microelectronic substrates and support members.
  18. Jiang,Tongbi, Method and apparatus for attaching microelectronic substrates and support members.
  19. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.
  20. Tay, Wuu Yean; Tan, Cher Khng Victor, Method for packaging microelectronic devices.
  21. Neo, Chee Peng; Tan, Hock Chuan; Chew, Beng Chye; Chai, Yih Ming; Tan, Kian Shing, Method of fabricating microelectronic component assemblies employing lead frames having reduced-thickness inner lengths.
  22. Akram, Salman; Hembree, David R., Methods and apparatuses for transferring heat from stacked microfeature devices.
  23. Akram, Salman; Hembree, David R., Methods and apparatuses for transferring heat from stacked microfeature devices.
  24. Rigg,Sidney B.; Watkins,Charles M.; Kirby,Kyle K.; Benson,Peter A.; Akram,Salman, Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices.
  25. Rigg,Sidney B.; Watkins,Charles M.; Kirby,Kyle K.; Benson,Peter A.; Akram,Salman, Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices.
  26. Chong, Chin Hui; Lee, Choon Kuan; Corisis, David J., Methods for making microelectronic die systems.
  27. Yean, Tay Wuu; Khng, Victor Tan Cher, Methods for packaging microelectronic devices.
  28. Lee, Choon Kuan; Chong, Chin Hui; Corisis, David J., Methods for packaging microelectronic devices and microelectronic devices formed using such methods.
  29. Lee, Choon Kuan; Chong, Chin Hui; Corisis, David J., Methods for packaging microelectronic devices and microelectronic devices formed using such methods.
  30. Lee, Choon Kuan; Chong, Chin Hui; Corisis, David J., Methods for packaging microelectronic devices and microelectronic devices formed using such methods.
  31. Benson,Peter A.; Watkins,Charles M., Methods for packaging microfeature devices and microfeature devices formed by such methods.
  32. Benson, Peter A.; Watkins, Charles M., Methods for packing microfeature devices and microfeature devices formed by such methods.
  33. Akram, Salman; Hembree, David R., Methods for transferring heat from stacked microfeature devices.
  34. Farnworth, Warren M.; Wood, Alan G., Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods.
  35. Farnworth, Warren M.; Wood, Alan G., Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods.
  36. Clyne, Craig T.; Fernandez, John C., Methods of adhering microfeature workpieces, including a chip, to a support member.
  37. Peng,Neo Chee; Chuan,Tan Hock; Chye,Chew Beng; Ming,David Chai Yih; Shing,Michael Tan Kian, Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths.
  38. Peng,Neo Chee; Chuan,Tan Hock; Chye,Chew Beng; Ming,David Chai Yih; Shing,Michael Tan Kian, Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths.
  39. Seng,Eric Tan Swee; Chung,Edmund Low Kwok, Microelectronic component assemblies with recessed wire bonds and methods of making same.
  40. Seng,Erin Tan Swee; Chung,Edmund Low Kwok, Microelectronic component assemblies with recessed wire bonds and methods of making same.
  41. Tan, Eric Swee Seng; Low, Edmund Kwok Chung, Microelectronic component assemblies with recessed wire bonds and methods of making same.
  42. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.
  43. Kweon, Young Do; Brooks, J. Michael; Jiang, Tongbi, Microelectronic devices.
  44. Yean,Tay Wuu; Khng,Victor Tan Cher, Microelectronic devices.
  45. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filing vias in microelectronic devices.
  46. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filling vias in microelectronic devices.
  47. Lee, Teck Kheng; Chai, David Yih Ming; Ng, Hong Wan, Microelectronic devices and microelectronic support devices, and associated assemblies and methods.
  48. Lee, Teck Kheng; Chai, David Yih Ming; Ng, Hong Wan, Microelectronic devices and microelectronic support devices, and associated assemblies and methods.
  49. Lee, Teck Kheng; Chai, David Yih Ming; Ng, Hong Wan, Microelectronic devices and microelectronic support devices, and associated assemblies and methods.
  50. Lee, Teck Kheng; Chai, David Yih Ming; Ng, Hong Wan, Microelectronic devices and microelectronic support devices, and associated assemblies and methods.
  51. Fee, Setho Sing, Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts.
  52. Fee, Setho Sing, Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts.
  53. Fee, Setho Sing, Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts.
  54. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung; Tay, Wuu Yean, Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods.
  55. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  56. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  57. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  58. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  59. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  60. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  61. Eng, Meow Koon; Chia, Yong Poo; Boon, Suan Jeung, Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods.
  62. Chong, Chin Hui; Lee, Choon Kuan; Corisis, David J., Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods.
  63. Rigg, Sidney B.; Watkins, Charles M.; Kirby, Kyle K.; Benson, Peter A.; Akram, Salman, Microelectronics devices, having vias, and packaged microelectronic devices having vias.
  64. Clyne, Craig T.; Fernandez, John C., Microfeature systems including adhered microfeature workpieces and support members.
  65. Lee, Teck Kheng; Lim, Andrew Chong Pei, Microfeature workpiece substrates having through-substrate vias, and associated methods of formation.
  66. Schwab, Matt E.; Brooks, J. Michael; Corisis, David J., Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices.
  67. Schwab, Matt E.; Corisis, David J.; Brooks, J. Michael, Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices.
  68. Schwab, Matt E.; Corisis, David J.; Brooks, J. Michael, Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices.
  69. Corisis, David J.; Chong, Chin Hui; Lee, Choon Kuan, Packaged microelectronic devices recessed in support member cavities, and associated methods.
  70. Corisis, David J.; Chong, Chin Hui; Lee, Choon Kuan, Packaged microelectronic devices recessed in support member cavities, and associated methods.
  71. Corisis, David J.; Chong, Chin Hui; Lee, Choon Kuan, Packaged microelectronic devices recessed in support member cavities, and associated methods.
  72. Schwab, Matt E.; Brooks, J. Michael; Corisis, David J., Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components.
  73. Schwab, Matt E.; Brooks, J. Michael; Corisis, David J., Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components.
  74. Schwab, Matt E.; Brooks, J. Michael; Corisis, David J., Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components.
  75. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  76. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  77. Kirby, Kyle K., Probe card for use with microelectronic components, and methods for making same.
  78. Seng, Eric Tan Swee, Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components.
  79. Seng,Eric Tan Swee, Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components.
  80. Kinsman,Larry D., Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same.
  81. Kinsman,Larry D., Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same.
  82. Jiang, Tongbi, Thermally conductive adhesive tape for semiconductor devices and method for using the same.
  83. Werner, Thomas; Aubel, Oliver; Feustel, Frank, Wafer with improved plating current distribution.
  84. Werner, Thomas; Aubel, Oliver; Feustel, Frank, Wafer with improved plating current distribution.
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