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Data processing device, method of executing a program and method of compiling 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
출원번호 US-0563369 (2000-05-03)
우선권정보 EP-0201425 (1999-05-06)
발명자 / 주소
  • Hoogerbrugge, Jan
  • Augusteijn, Alexander
출원인 / 주소
  • Koninklijke Philips Electronics N.V.
대리인 / 주소
    Pietrowski, Daniel J.
인용정보 피인용 횟수 : 54  인용 특허 : 7

초록

A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A detector detects whether a same memory location is addressed by a first and second memory address used to access memory for a first and se

대표청구항

A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A detector detects whether a same memory location is addressed by a first and second memory address used to access memory for a first and se

이 특허에 인용된 특허 (7)

  1. Panwar Ramesh ; Chidambaran P.K. ; Hetherington Ricky C., Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine.
  2. Hesson James H. (Chittenden County VT) LeBlanc Jay (Chittenden County VT) Ciavaglia Stephen J. (Chittenden County VT), Apparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatc.
  3. Moreno Jaime Humberto ; Moudgill Mayan, Method and apparatus for reordering memory operations in a processor.
  4. Abramson Jeffrey M. (Aloha OR) Akkary Haitham (Portland OR) Glew Andrew F. (Hillsboro OR) Hinton Glenn J. (Portland OR) Konigsfeld Kris G. (Portland OR) Madland Paul D. (Beaverton OR) Papworth David , Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order.
  5. Afsar Muhammad ; Freymuth Christopher Anthony, Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor.
  6. Konigsburg Brian R ; Muhich John Stephen ; Thatcher Larry Edward ; White Steven Wayne, Support for out-of-order execution of loads and stores in a processor.
  7. Isaman David L., System and method of processing instructions for a processor.

이 특허를 인용한 특허 (54)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Ramchandran,Amit, Cache for instruction set architecture using indexes to achieve compression.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Kirsch, Graham, Flexible results pipeline for processing element.
  25. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  26. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  27. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
  31. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  35. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  36. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  45. Yamamoto, Kanta, Packet switching system.
  46. Kirsch, Graham, Processing element and method connecting registers to processing logic in a plurality of configurations.
  47. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  48. Wang, Hong; Aamodt, Tor; Hammarlund, Per; Shen, John; Tian, Xinmin; Girkar, Milind; Wang, Perry; Liao, Steve Shih-wei, Safe store for speculative helper threads.
  49. Wang, Hong; Aamodt, Tor M.; Marcuello, Pedro; Stark, IV, Jared W.; Shen, John P.; Gonzalez, Antonio; Hammarlund, Per; Hoflehner, Gerolf F.; Wang, Perry H.; Liao, Steve Shih-wei, Speculative multi-threading for instruction prefetch and/or trace pre-build.
  50. Wang, Hong; Aamodt, Tor M.; Marcuello, Pedro; Stark, IV, Jared W.; Shen, John P.; González, Antonio; Hammarlund, Per; Hoflehner, Gerolf F.; Wang, Perry H.; Liao, Steve Shih-wei, Speculative multi-threading for instruction prefetch and/or trace pre-build.
  51. Master,Paul L.; Watson,John, Storage and delivery of device features.
  52. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  53. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  54. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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