초록 ▼

A hybrid vehicle control apparatus controls an engine that rotates at least one first wheel and a mechanically independent electric motor that rotates at least one second wheel. The hybrid vehicle control apparatus stabilizes the vehicle driving performance when drive forces are obtained from both t

A hybrid vehicle control apparatus controls an engine that rotates at least one first wheel and a mechanically independent electric motor that rotates at least one second wheel. The hybrid vehicle control apparatus stabilizes the vehicle driving performance when drive forces are obtained from both the engine and the electric motor. Thus, the hybrid vehicle control apparatus stabilizes 4WD travel over a wide range using an engine and a comparatively small electric motor. The target front (motor-driven) wheel drive torque is calculated by subtracting the target rear (engine-driven) wheel drive torque from the total target drive torque. Meanwhile, the motor torque upper limit value is estimated from the motor rotational speed. If the front wheel target drive torque exceeds the motor torque upper limit value, the drive torque ΔT, which corresponds to the amount by which the motor torque is insufficient, is added to the rear wheel target drive torque.

대표청구항 ▼

A hybrid vehicle control apparatus controls an engine that rotates at least one first wheel and a mechanically independent electric motor that rotates at least one second wheel. The hybrid vehicle control apparatus stabilizes the vehicle driving performance when drive forces are obtained from both t

A hybrid vehicle control apparatus controls an engine that rotates at least one first wheel and a mechanically independent electric motor that rotates at least one second wheel. The hybrid vehicle control apparatus stabilizes the vehicle driving performance when drive forces are obtained from both the engine and the electric motor. Thus, the hybrid vehicle control apparatus stabilizes 4WD travel over a wide range using an engine and a comparatively small electric motor. The target front (motor-driven) wheel drive torque is calculated by subtracting the target rear (engine-driven) wheel drive torque from the total target drive torque. Meanwhile, the motor torque upper limit value is estimated from the motor rotational speed. If the front wheel target drive torque exceeds the motor torque upper limit value, the drive torque ΔT, which corresponds to the amount by which the motor torque is insufficient, is added to the rear wheel target drive torque. a plurality of buffer circuits for at least one of inputting and outputting; a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits; and an internal circuit electrically connected to the plurality of buffer circuits, wherein one terminal T1of the plurality of terminals corresponds to two circuits C1and C2of the plurality of buffer circuits, and wherein the terminal T1is selectively connected to the circuit C1by a part of the plurality of interconnecting lines. 16. The semiconductor chip as defined in claim 15, wherein another terminal T1Aof the plurality of terminals which is positioned symmetrically to the terminal T1with respect to a line corresponds to two circuits C1Aand C2Aof the plurality of buffer circuits, wherein the two circuits C1Aand C2Aare identical with the two circuits C1and C2at least in design, and wherein the terminal T1Ais selectively connected to the circuit C2Aby a part of the plurality of interconnecting lines. 17. The semiconductor chip as defined in claim 15, wherein each of even number of terminals of the plurality of terminals which corresponds to a plurality of signals for forming at least a part of one information is connected to any one of the plurality of buffer circuits and the even number of terminals are arranged symmetrically with respect to a line. 18. A semiconductor chip comprising: a plurality of terminals; a plurality of buffer circuits for at least one of inputting and outputting; a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits; and an internal circuit electrically connected to the plurality of buffer circuits, wherein each of the plurality of terminals is connected to any one of the plurality of buffer circuits by a part of the plurality of interconnecting lines, and wherein the plurality of buffer circuits are arranged in a line at a central portion of the semiconductor chip. 19. The semiconductor chip as defined in claim 18, wherein the plurality of buffer circuits are arranged along a center line of the semiconductor chip. 20. A semiconductor device comprising a plurality of stacked semiconductor chips, wherein each of the semiconductor chips is the semiconductor chip as defined in claim 15. 21. A semiconductor device comprising a plurality of stacked semiconductor chips, wherein at least one of the semiconductor chips is the semiconductor chip as defin