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A method and apparatus for testing integrated circuits is described. The method and apparatus provide a nearly constant power supply current load on the test power supply, and a nearly constant thermal load on the cooling system. This promotes more reliable and repeatable testing of production integ

A method and apparatus for testing integrated circuits is described. The method and apparatus provide a nearly constant power supply current load on the test power supply, and a nearly constant thermal load on the cooling system. This promotes more reliable and repeatable testing of production integrated circuits. A dummy load, in thermal contact with a device under test and the cooling system, consumes a value of current complementary to the current consumed by the device under test, which is under the control of a series of enhanced test vectors.

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1. A system, comprising: a cooling system; a cold plate operatively coupled with the cooling system, the cold plate to contact a first device under test positioned in a test socket; a dummy load attached to the cold plate and controlled by electronic signals produced by a register, the dummy lo

1. A system, comprising: a cooling system; a cold plate operatively coupled with the cooling system, the cold plate to contact a first device under test positioned in a test socket; a dummy load attached to the cold plate and controlled by electronic signals produced by a register, the dummy load configured to consume a complimentary first current to a second current generated in the first device under test, wherein the register produces the electronic signals in response to a load control vector associated with a test vector. 2. The system of claim 1 wherein the electronic signals control a plurality of switches of the dummy load. 3. The system of claim 2, wherein said switches control current through a plurality of resistors. 4. The system of claim 1, wherein said dummy load is mounted between said cold plate and said first device under test. 5. A system as in claim 1, wherein the test vector is a digital word comprised of a first plurality of bits and sent by a test computer to the register via an interconnect coupling the computer to the register. 6. A system as in claim 5, wherein the first plurality of bits corresponds to a second plurality of register locations. 7. A system as in claim 6, wherein a bit of the plurality of bits contains a zero which may be interpreted by a conventional register of the corresponding plurality of register locations as a command to send a logic low electronic signal via the test socket to a corresponding pin of the device under test. 8. A system as in claim 5, wherein the load control vector further comprises: a second plurality of bits tagged onto the test vector. 9. A system as in claim 8, wherein current consumption in the dummy load is controlled by the load control vector when the bits comprising the load control vector are loaded into a corresponding plurality of register locations. 10. A system as in claim 1, wherein the test vector controls a current consumed by the device under test. 11. A system as in claim 1, wherein the load control vector controls a current consumed by the dummy load. 12. A method, comprising: connecting a dummy load controlled by electronic signals produced a register with a device under test positioned in a test socket; connecting a cold plate to the dummy load, the cold plate operatively coupled with a cooling system; exhausting heat from said cold plate utilizing the cooling system; providing a complimentary first current to the dummy load when a second current is applied to the device under test; and applying a load control vector associated with a test vector to the register to produce the electronic signals from the register. 13. A method as in claim 12, wherein applying a load control vector associated with a test vector to the register further comprises: forming the test vector in a computer as a digital word comprised of a first plurality of bits; forming the load control vector in the computer as a second plurality of bits; and tagging the second plurality of bits onto the first plurality of bits.