United States of America as represented by the Administrator of the National Aeronautics and Space Administration
대리인 / 주소
Ro, Theodore U.
인용정보
피인용 횟수 :
3인용 특허 :
10
초록▼
System and methods are disclosed for passively determining the location of a moveable transmitter utilizing a pair of phase shifts at a receiver for extracting a direction vector from a receiver to the transmitter. In a preferred embodiment, a phase difference between the transmitter and receiver is
System and methods are disclosed for passively determining the location of a moveable transmitter utilizing a pair of phase shifts at a receiver for extracting a direction vector from a receiver to the transmitter. In a preferred embodiment, a phase difference between the transmitter and receiver is extracted utilizing a noncoherent demodulator in the receiver. The receiver includes an antenna array with three antenna elements, which preferably are patch antenna elements spaced apart by one-half wavelength. Three receiver channels are preferably utilized for simultaneously processing the received signal from each of the three antenna elements. Multipath transmission paths for each of the three receiver channels are indexed so that comparisons of the same multipath component are made for each of the three receiver channels. The phase difference for each received signal is determined by comparing only the magnitudes of received and stored modulation signals to determine a winning modulation symbol.
대표청구항▼
System and methods are disclosed for passively determining the location of a moveable transmitter utilizing a pair of phase shifts at a receiver for extracting a direction vector from a receiver to the transmitter. In a preferred embodiment, a phase difference between the transmitter and receiver is
System and methods are disclosed for passively determining the location of a moveable transmitter utilizing a pair of phase shifts at a receiver for extracting a direction vector from a receiver to the transmitter. In a preferred embodiment, a phase difference between the transmitter and receiver is extracted utilizing a noncoherent demodulator in the receiver. The receiver includes an antenna array with three antenna elements, which preferably are patch antenna elements spaced apart by one-half wavelength. Three receiver channels are preferably utilized for simultaneously processing the received signal from each of the three antenna elements. Multipath transmission paths for each of the three receiver channels are indexed so that comparisons of the same multipath component are made for each of the three receiver channels. The phase difference for each received signal is determined by comparing only the magnitudes of received and stored modulation signals to determine a winning modulation symbol. r and hardware modulator to generate a signal of desired waveform for infrared transmission. The integrated circuit also includes a multiplexer for receiving the signal of desired waveform from the hardware modulator and a data output signal in producing a selected output signal responsive to a control signal. The integrated circuit further includes an output buffer coupled to the multiplexer for transferring data to an output terminal. that increases in resistance as a function of the applied voltage; a second circuit element having a resistivity that decreases in resistance as a function of the applied voltage; said first circuit element connected in parallel with said second circuit element and providing a signal to the oscillator; a plurality of odd numbered serially connected inverters, each inverter having an input and an output with the output of one inverter connected to the input of an adjacent inverter with the output of the last inverter connected to the input of the first inverter; each inverter comprising: a first PMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; a first NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said second terminal of said first PMOS transistor connected to the first terminal of said first NMOS transistor and forming said output; said gate of said first PMOS transistor connected to the gate of said first NMOS transistor and forming said input; a second NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first terminal of said second NMOS transistor connected to the second terminal of said first NMOS transistor; and said gate of said second NMOS transistor of said plurality of inverters being connected together to said first terminal of said MOS transistor, wherein said first circuit element is an inductor. 9. A current source for an oscillator comprising: at least one resistor circuit including a switch and a resistor coupled in series with said switch; and a MOS transistor having a first terminal connected to a supply voltage and a second terminal being at a voltage greater than a ground voltage and with a channel therebetween, and a gate for controlling the current flow therebetween, said at least one resistor circuit being connected in parallel to said first terminal and said second terminal, a voltage connected to said gate to maintain said MOS transistor being conductive independent of whether said switch is conductive. 10. The current source of claim 9 wherein said MOS transistor is of P type and said voltage is ground. 11. The current source of claim 9 wherein said MOS transistor is of N type and said voltage is Vdd. 12. An oscillator comprising: a current source including: at least one resistor circuit including a switch and a resistor coupled in series with said switch, and a MOS transistor having a first terminal connected to a supply voltage and a second terminal being at a voltage greater than a ground voltage with a channel therebetween, and a gate for controlling the current flow therebetween, said at least one resistor circuit being connected in parallel to said first terminal and said second terminal, a voltage connected to said gate to maintain said MOS transistor being conductive independent of whether said switch is conductive; and a plurality of odd numbered serially connected inverters, each inverter having an input and an output with the output of one inverter connected to the input of an adjacent inverter with the output of the last inverter connected to the input of the first inverter; each inverter comprising: a first PMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; a first NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said second terminal of said first PMOS transistor connected to the first terminal of said first NMOS transistor and forming said output; said gate of said first PMOS transistor connected to the gate of said first NMOS transistor and forming said input; a second NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first terminal of said second NMOS transistor connected to the second terminal of said first NMOS transistor, and said gate of said second NMOS transistor of said plurality of inverters being connected together to said fist terminal of said MOS transistor. 13. The oscillator of claim 12 wherein said MOS transistor is of P type and said voltage is ground. 14. The oscillator of claim 12 wherein said MOS transistor is of N type and said voltage is Vdd. 15. The current source of claim 7 wherein said second circuit element is an MOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first and second terminal connected in parallel with said first circuit element; and a voltage source connected to said gate to maintain said MOS transistor in a conduction state. 16. The current source of claim 15 wherein said MOS transistor is of P type and said voltage is ground. 17. The current source of claim 15 wherein said MOS transistor is of N type and said voltage is Vdd. 18. The oscillator of claim 8 wherein said second circuit element is an MOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first and second terminal connected in parallel with said first circuit element; and a voltage source connected to said gate to maintain said MOS transistor in a conduction state. 19. The oscillator of claim 18 wherein said MOS transistor is of P type and said voltage is ground. 20. The oscillator of claim 18 wherein said MOS transistor is of N type and said voltage is Vdd. 21. A current source for an oscillator comprising: a resistor; a MOS transistor of P type having a first terminal connected to a supply voltage and a second terminal being at a voltage greater than a ground voltage and with a channel therebetween, and a gate for controlling the current flow therebetween connected to a ground voltage to maintain said MOS transistor in a conduction state; and said first terminal and second terminal connected in parallel with said resistor. 22. A current source for an oscillator comprising: a resistor; a MOS transistor of N type having a first terminal connected to a Vdd voltage and a second terminal being at a voltage greater than a ground voltage and with a channel therebetween, and a gate for controlling the current flow therebetween connected to said Vdd voltage to maintain said MOS transistor in a conduction state; and said first terminal and second terminal connected in parallel with said resistor. 23. An oscillator comprising: a current source comprising: a resistor; a MOS transistor of P type having a first terminal connected to a supply voltage and a second terminal being at a voltage greater than a ground voltage and with a channel therebetween, and a gate for controlling the current flow therebetween connected to a ground voltage to maintain said MOS transistor in a conduction state, and said first terminal and second terminal connected in parallel with said resistor; and a plurality of odd numbered serially connected inverters, each inverter having an input and an output with the output of one inverter connected to the input of an adjacent inverter with the output of the last inverter connected to the input of the first inverter; each inverter comprising: a first PMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; a first NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said second terminal of said first PMOS transistor connected to the first terminal o f said first NMOS transistor and forming said output; said gate of said first PMOS transistor connected to the gate of said first NMOS transistor and forming said input; a second NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first terminal of said second NMOS transistor connected to the second terminal of said first NMOS transistor; and said gate of said second NMOS transistor of said plurality of inverters being connected together to said first terminal of said MOS transistor. 24. An oscillator comprising: a current source comprising: a resistor; a MOS transistor of N type having a first terminal connected to a supply voltage and a second terminal being at a voltage greater than a ground voltage and with a channel therebetween, and a gate for controlling the current flow therebetween connected to a Vdd voltage to maintain said MOS transistor in a conduction state, and said first terminal and second terminal connected in parallel with said resistor; and a plurality of odd numbered serially connected inverters, each inverter having an input and an output with the output of one inverter connected to the input of an adjacent inverter with the output of the last inverter connected to the input of the first inverter; each inverter comprising: a first PMOS transistor having a first terminal and a second thermal with a channel therebetween, and a gate for controlling the current flow therebetween; a first NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said second terminal of said first PMOS transistor connected to the first terminal of said first NMOS transistor and forming said output; said gate of said first PMOS transistor connected to the gate of said first NMOS transistor and forming said input; a second NMOS transistor having a first terminal and a second terminal with a channel therebetween, and a gate for controlling the current flow therebetween; said first terminal of said second NMOS transistor connected to the second terminal of said first NMOS transistor; and said gate of said second NMOS transistor of said plurality of inverters being connected together to said first terminal of said MOS transistor.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (10)
Antonio Franklin P. (Del Mar CA) Gilhousen Klein S. (Bozeman MT) Wolf Jack K. (La Jolla CA) Zehavi Ephraim (San Diego CA), Adaptive sectorization in a spread spectrum communication system.
Zehavi Ephraim (Haifa ILX) Carter Stephen S. (San Diego CA) Gilhousen Klein S. (Bozeman MT), Method and apparatus for using full spectrum transmitted power in a spread spectrum communication system for tracking in.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.