초록

An apparatus for the continuous measurement of glucose and lactate in interstitial fluids including a glucose measurement cell, an A/D conversion block, a memory block and a bi-directional communication between the interface block and an external calculation unit.

대표청구항 ▼

An apparatus for the continuous measurement of glucose and lactate in interstitial fluids including a glucose measurement cell, an A/D conversion block, a memory block and a bi-directional communication between the interface block and an external calculation unit. y device coupled to said processor,

An apparatus for the continuous measurement of glucose and lactate in interstitial fluids including a glucose measurement cell, an A/D conversion block, a memory block and a bi-directional communication between the interface block and an external calculation unit. y device coupled to said processor, said nonvolatile memory device comprising: an array of memory cells; and a write state machine for controlling operations on said array of memory cells; said write state machine containing instructions for performing said operations on said array of memory cells, said instructions being stored in read only memory associated with said write state machine, said write state machine being adapted to suspend an execution of one of said operations during an action on a block in the flash memory which is not being accessed by said write state machine. 19. The system of claim 18, wherein said read only memory is internal to said write state machine. 20. The system of claim 18, wherein said read only memory is integrated on the same chip as said write state machine. 21. The system of claim 18, wherein said array of cells is an array of flash memory cells. 22. The system of claim 18, wherein said read only memory comprises at least one instruction to read data from at least one cell of said array of memory cells. 23. The system of claim 22, wherein said read only memory comprises at least one instruction to suspend said at least one instruction to read data. 24. The system of claim 18, wherein said read only memory comprises at least one write instruction to write data to at least one cell of said array of memory cells. 25. The system of claim 24, wherein said read only memory comprises at least one instruction to suspend said at least one instruction to write data. 26. The system of claim 18, wherein said read only memory comprises at least one instruction to erase data from said array of memory cells. 27. The system of claim 18, wherein said read only memory comprises at least one instruction to program at least one cell of said array of memory cells. 28. The system of claim 18, wherein said write state machine comprises a microcontroller including read only memory. 29. The system of claim 18, wherein said write state machine comprises an address counter. 30. The system of claim 18, wherein said write state machine comprises an instruction decoder. 31. The system of claim 18, wherein said write state machine comprises an internal data latch. 32. The system of claim 18, wherein said write state machine comprises at least one data latch. 33. A method of operating a nonvolatile memory system for storing data values comprising the acts of: performing a portion of an operation on an array of flash memory cells with a write state machine which is responsive to instructions stored in a read only memory associated with said write state machine; suspending said operation; performing an act on a block of said flash memory cells which is not being accessed by said write state machine; and completing said operation. 34. The method of claim 33 wherein read only memory is internal to said write state machine. 35. The method of claim 33 further wherein said read only memory is on the same chip as said write state machine. 36. The method of claim 33 further comprising loading at least one instruction to read data from at least one cell of said array of memory cells into said read only memory. 37. The method of claim 36 further comprising loading at least one instruction to suspend said at least one instruction to read data into said read only memory. 38. The method of claim 33 further comprising loading at least one write instruction to write data to at least one cell of said array of memory cells into said read only memory. 39. The method of claim 38 further comprising loading at least one instruction to suspend said at least one instruction to write data into said read only memory. 40. The method of claim 33 further comprising loading at least one write instruction to erase data from said array of memory cells into said read only memory. 41. The method of claim 33 further comprising loading at least one write instruction to program at least one cell of said array of memory cells into said read only