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Method and apparatus for communicating between multiple functional units in a computer environment 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0235025 (1999-01-21)
발명자 / 주소
  • Greenfield, Zvi
출원인 / 주소
  • Analog Devices, Inc.
대리인 / 주소
    Wolf, Greenfield & Sacks, PC
인용정보 피인용 횟수 : 41  인용 특허 : 26

초록

A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functio

대표청구항

A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functio

이 특허에 인용된 특허 (26)

  1. Koehler Robert J. (Cupertino CA) Bayliss John A. (Portland OR), Apparatus and method for cooperative and concurrent coprocessing of digital information.
  2. Leshem Eli, Bus arbitration system having a pair of logic networks to control data transfer between a memory and a pair of buses.
  3. Sheafor Stephen James ; Wei James Yuan, Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method.
  4. Thomas James H. (Plantation) Smith Royston L. (Plantation FL) Ward William P. (Poway CA), Bus structure for overlapped data transfer.
  5. Higaki Nobuo (Osaka JPX) Matsuzaki Toshimichi (Minou JPX), Data processing apparatus having bus switches for selectively connecting buses to improve data throughput.
  6. Datwyler Wayne C. (Laguna Niguel CA) Tran Dan T. (Laguna Niguel CA) Ha Long V. (Walnut CA), Dual bus adaptable data path interface system.
  7. Sheth Jayesh V. (Mission Viejo CA) Harris Craig W. (Lake Forest CA) White Theodore C. (Tustin CA) Nguyen Kha (Anaheim CA) Wong Chung W. (Dana Point CA) Cowgill Richard A. (Lake Forest CA), Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O device.
  8. Yanai Moshe ; Vishlitzky Natan ; Alterescu Bruno ; Castel Daniel, Dual bus computer architecture utilizing distributed arbitrators and method of using same.
  9. Tran Dan Trong ; Ricci Paul Bernard ; Sheth Jayesh Vrajlal ; White Theodore Curt ; Cowgill Richard Allen, Dual bus system with multiple processors having data coherency maintenance.
  10. Kalish David Mark (Laguna Niguel CA) Marrash Russell Lee (Irvine CA) Whitlock Gary Carl (Mission Viejo CA) Nguyen Kha (Anaheim CA), Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses.
  11. Thacker Charles P. (Palo Alto CA) Hartwell David (Boxboro MA), Dynamic arbitration for system bus control in multiprocessor data processing system.
  12. Fernando Roshan (Portland OR), Fractional speed bus coupling.
  13. Kwon Hwan-Woo,KRX, Hierarchical dual bus architecture for use in an electronic switching system employing a distributed control architecture.
  14. Clark Alan D. (Near Devizes GBX), Hybrid data communications systems.
  15. Haines Ralph Warren ; O'Neill Dan Craig ; Pries Stephen C. ; Miller William V. ; Waterson Kent B. ; Weinman David S. ; Shay Michael J. ; Pang Jianhua Helen ; Herrington Daniel R. ; Marley Brian J. ; , Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access an.
  16. Tanji Masayuki (Hitachi JPX) Miyazaki Yoshihiro (Hitachi JPX) Fukumaru Hiroaki (Hitachi JPX) Yamaguchi Syoji (Hitachi JPX) Masui Koji (Hitachi JPX) Ogawa Hisao (Hitachi JPX), Method and apparatus for controlling dual bus system.
  17. Somer Gregory B., Method and apparatus for performing collision detection and arbitration within an expansion bus having multiple transmis.
  18. Miyazaki Yoshihiro (Hitachi JPX) Takahashi Yoshiaki (Mito JPX) Araoka Manabu (Hitachi JPX) Takaya Soichi (Hitachi JPX) Fukumaru Hiroaki (Hitachi JPX), Method for controlling multiple common memories and multiple common memory system.
  19. Bass Brian Mitchell ; Henderson Douglas Ray ; Heron Karen Park ; Kidd Jeffrey Wayne ; Ku Edward Hau-chun ; Lingafelt ; Sr. Charles Steven ; Reiss Loren Blair, Method for modifying an existing computer bus to enhance system performance.
  20. Hamaguchi Kazumasa (Kawasaki JPX) Shibayama Shigeki (Yokohama JPX), Method of utilizing common buses in a multiprocessor system.
  21. Goto Harutaka (Yokohama JPX), Microprocessor with two groups of internal buses.
  22. Ingerman Donald (Boca Raton FL), Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than.
  23. Adamson Alan P. ; Sandison Thomas M. ; Williams Charles E., Physical-to-logical bus mapping scheme for computer systems having multiple PCI bus configuration.
  24. Datwyler Wayne C. (Laguna Niguel CA) Ricci Paul B. (Laguna Niguel CA), Transmission logic apparatus for dual bus network.
  25. Kenny John D. ; Shah Pranay D., Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus.
  26. Lambrecht J. Andrew ; Hartmann Alfred C., Variable latency and bandwidth communication pathways.

이 특허를 인용한 특허 (41)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  10. Jung, Seok-yoon; Kim, Il-san; Park, Jin-hong; Han, Tack-don, Bus arbitration system, medium, and method.
  11. Yamaguchi, Takao; Yoshida, Atsushi; Ishii, Tomoki; Tokutsu, Satoru, Bus system for semiconductor circuit.
  12. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  13. Bailey,Robert L; Howard,Brian D; Wynne,Lesley B, Dynamically allocating devices to buses.
  14. Kulkarni,Milind Manohar; Thomas,Bijo, Electronic data processing circuit that transmits packed words via a bus.
  15. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  16. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  17. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  18. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  19. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  21. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
  22. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  23. Jobs, Jeffrey R.; Stenglein, Thomas A., Memory hub architecture having programmable lane widths.
  24. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  25. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  26. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  27. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  28. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  29. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  30. Griessbach,Robert, Method for exchanging data between a plurality of subscribers by means of a data bus.
  31. Carpenter,Billy R., Multi-redundant inlaid wiring harness.
  32. Takeuchi,Toshiki; Igura,Hiroyuki, Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry.
  33. Floman,Matti, Operating memory components.
  34. Fanning, Blaise B., Point-to-point busing and arrangement.
  35. Leijten,Jeroen Anton Johan, Programmed access latency in mock multiport memory.
  36. Riley, Dwight D., Sharing legacy devices in a multi-host environment.
  37. Riley, Dwight D., System and method for multi-host sharing of a single-host device.
  38. Janzen, Jeffery W., System and method for optimizing interconnections of components in a multichip memory module.
  39. Ryan, Kevin J., System and method for optimizing interconnections of memory devices in a multichip module.
  40. James, Ralph; Jeddeloh, Joe, System and method for transmitting data packets in a computer system having a memory hub architecture.
  41. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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