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다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0594285 (2000-06-15) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 936 인용 특허 : 258 |
A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agen
A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent.
A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agen
A sensor utilizing a non-leachable or diffusible redox mediator is described. The sensor includes a sample chamber to hold a sample in electrolytic contact with a working electrode, and in at least some instances, the sensor also contains a non-leachable or a diffusible second electron transfer agent. The sensor and/or the methods used produce a sensor signal in response to the analyte that can be distinguished from a background signal caused by the mediator. The invention can be used to determine the concentration of a biomolecule, such as glucose or lactate, in a biological fluid, such as blood or serum, using techniques such as coulometry, amperometry, and potentiometry. An enzyme capable of catalyzing the electrooxidation or electroreduction of the biomolecule is typically provided as a second electron transfer agent. eaken said first transistor so that said data bit on said bit line can switch the state of said second inverter, and thereby switching the state of said bit latch. 3. The bit latch of claim 1 wherein said first transistor is an NMOS transistor. 4. The bit latch of claim 3 wherein said control circuit comprises a control transistor having: a third drain/source connected to said third terminal of said first inverter; a fourth drain/source connected to ground; and a first gate receiving a control signal; wherein, in response to said data bit appearing on said bit line, said control signal barely turns on said control transistor so as to weaken said first inverter so that said data bit on said bit line can switch the state of said second inverter, and thereby switching the state of said bit latch. 5. The bit latch of claim 4 wherein said control transistor is an NMOS transistor. 6. The bit latch of claim 5 wherein said first and second inverters are CMOS inverters. 7. The bit latch of claim 1 wherein said control circuit comprises a control transistor having: a first drain/source connected to said third terminal of said first inverter; a second drain/source connected to ground; and a first gate receiving a control signal; wherein, in response to said data bit appearing on said bit line, said control signal barely turns on said control transistor so a to weaken said first inverter so that said data bit on said bit line can switch the state of said second inverter, and thereby switching the state of said bit latch. 8. The bit latch of claim 7 wherein said control transistor is an NMOS transistor. 9. The bit latch of claim 8 wherein said first and second inverters are CMOS inverters. 10. The bit latch of claim 1 wherein said means for generating a control signal for said control circuit further comprises: said switch transistor being an NMOS transistor having a source connected an input mode signal, its drain connected to a mirror transistor, and a gate connected to an electrical ground; said mirror transistor being an NMOS transistor having a gate and drain tied together; a PMOS load transistor having a source connected to said gate of said mirror transistor, a gate connected to the electrical ground, and a drain connected to a voltage supply; and a PMOS pull up transistor having a gate connected to the gate to said switch transistor, a drain connected to the supply voltage, and a source connected to the gate of said mirror transistor and forming said control signal. 11. A method of storing a data bit on a bit line into a bit latch, said method comprising the steps of: providing said bit latch which comprises a pair of first and second cross-coupled inverters, said bit latch having a first and second states, said first inverter having a third and fourth states corresponding to said first and second states of said bit latch, respectively, said second inverter having a fifth and sixth states corresponding to said first and second states of said bit latch, respectively, said first inverter having a first input node and a first output node, said first output node being connected to said bit line, said second inverter having a second input node and a second output node, said second input node being connected to said first output node, said second output node being connected to said first input node; resetting said bit latch to said first state, whereby said first inverter being reset to said third state, and second inverter being reset to said fifth state; applying said data bit to said bit line; and weakening said first inverter so that said data bit on said bit line can switch said second inverter from said fifth state to said sixth state, thereby causing said first inverter to switch from said third state to said fourth state, whereby said bit latch switches from said first state to said second state representing the storage of said data bit in said bit latch. 12. The method of claim 11 further compri sing the step of strengthening said first inverter after said data bit has been stored in said bit latch, whereby said data bit is firmly stored in said bit latch. 13. The method of claim 12 wherein the step of providing said bit latch comprises the step of providing said first inverter with a first transistor, said first transistor having: a first source/drain connected to said first output node; and a second source/drain. 14. The method of claim 13 wherein the step of weakening said first inverter comprises the step of providing a high resistance between said second source/drain of said first inverter and ground. 15. The method of claim 14 wherein the step of providing a high resistance comprises the steps of: providing a control transistor to couple said second source/drain of said first inverter to ground; and barely turning on said control transistor to provide said high resistance between said second source/drain of said first inverter and ground. 16. The method of claim 15 wherein the step of strengthening said first inverter comprises the step of strongly turning on said control transistor to provide a low resistance between said second source/drain of said first inverter and ground, whereby said data bit is firmly stored in said bit latch. 17. The method of claim 15 wherein the step of barely turning on said control transistor comprises the step of using a mirror transistor to generate a control signal to a gate of said control transistor so as to barely turn on said control transistor. 18. The method of claim 11 wherein the step of providing said bit latch comprises the step of providing said first inverter with a first transistor, said first transistor having: a first source/drain connected to said first output node; and a second source/drain. 19. The method of claim 18 wherein the step of weakening said first inverter comprises the step of providing a high resistance between said second source/drain of said first inverter and ground. 20. The method of claim 19 wherein the step of providing a high resistance comprises the steps of: providing a control transistor to couple said second source/drain of said first inverter to ground; and barely turning on said control transistor to provide said high resistance between said second source/drain of said first inverter and ground. 21. The method of claim 20 wherein the step of strengthening said first inverter comprises the step of strongly turning on said control transistor to provide a low resistance between said second source/drain of said first inverter and ground, whereby said data bit is firmly stored in said bit latch.
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