A solder alloy containing indium, lead, silver and copper as its alloying constituents, and a soldering process employing the solder alloy. The solder alloy consists essentially of, by weight, about 50% to about 65% indium, about 0.5% to about 3.0% silver, up to about 3.0% copper, the balance lead a
A solder alloy containing indium, lead, silver and copper as its alloying constituents, and a soldering process employing the solder alloy. The solder alloy consists essentially of, by weight, about 50% to about 65% indium, about 0.5% to about 3.0% silver, up to about 3.0% copper, the balance lead and incidental impurities. The alloy preferably has a solidus temperature in a range of about 173° C. to about 178° C., and a liquidus temperature in a range of about 187° C. to about 196° C. As such, the alloy can be used in a reflow process with a peak reflow temperature of about 220° C. to about 240° C., and is therefore compatible with most circuit components and can be simultaneously reflowed with 63Sn-37Pb solder.
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1. A soldering process comprising the steps of: depositing on an interconnect pad of an integrated circuit device a solder alloy consisting essentially of, by weight, about 50% to about 60.0% indium, about 0.5% to about 3.0% silver, 0.0% to about 3.0% copper, the balance lead and incidental impur
1. A soldering process comprising the steps of: depositing on an interconnect pad of an integrated circuit device a solder alloy consisting essentially of, by weight, about 50% to about 60.0% indium, about 0.5% to about 3.0% silver, 0.0% to about 3.0% copper, the balance lead and incidental impurities; and then reflowing the solder alloy to form a solder bump on the interconnect pad, the solder bump comprising a layer of silver-indium and/or copper-indium intermetallic compound contacting the interconnect pad as a result of the reflowing step. 2. A soldering process according to claim 1, wherein the solder alloy has a solidus temperature in a range of about 173° C. to about 178° C. 3. A soldering process according to claim 1, wherein the solder alloy has a liquidus temperature in a range of about 187° C. to about 196° C. 4. A soldering process according to claim 1, wherein the silver content is about 1.0 to about 2.0 weight percent of the solder alloy, and the copper content is about 1.0 to about 2.0 weight percent of the solder alloy. 5. A soldering process according to claim 1, wherein the silver content is about 1.0 weight percent of the solder alloy, and the copper content is about 0.5 to about 2.0 weight percent of the solder alloy. 6. A soldering process according to claim 1, wherein the silver content is about 2.0 weight percent of the solder alloy, and the copper content is up to about 2.0 weight percent of the solder alloy. 7. A soldering process according to claim 1, wherein the indium content is about 53.5 to about 54.5 weight percent of the solder alloy. 8. A soldering process according to claim 1, further comprising the step of registering the solder bump with a metal trace on a laminate substrate, and then reflowing the solder bump to form a solder joint that metallurgically joins the interconnect pad to the metal trace so as to attach the integrated circuit device to the laminate substrate. 9. A soldering process according to claim 8, wherein the layer of silver-indium and/or copper-indium intermetallic compound contacts the interconnect pad following the step of reflowing the solder bump. 10. A soldering process comprising the steps of: depositing on an interconnect pad of an integrated circuit device a solder alloy consisting essentially of, by weight, 50% to 65% indium, 0.5% to 3.0% silver, 0.0% to 3.0% copper, the balance lead and incidental impurities, the solder alloy having a solidus temperature in a range of about 173° C. to about 178° C. and a liquidus temperature in a range of about 187° C. to about 196° C.; reflowing the solder alloy to form a solder bump on the interconnect pad, the solder bump comprising a layer of silver-Indium and/or copper-indium intermetallic compound contacting the interconnect pad as a result of the reflowing step; registering the solder bump with a metal trace on a laminate substrate; and then reflowing the solder bump to form a solder joint that metallurgically joins the interconnect pad to the metal trace so as to attach the integrated circuit device to the laminate substrate, the layer of silver-indium and/or copper-indium intermetallic compound contacting the interconnect pad. 11. A soldering process according to claim 10, wherein the silver content is about 1.0 to about 2.0 weight percent of the solder alloy, and the copper content is about 1.0 to about 2.0 weight percent of the solder alloy. 12. A soldering process according to claim 10, wherein the silver content is about 1.0 weight percent of the solder alloy, and the copper content is about 0.5 to about 2.0 weight percent of the solder alloy. 13. A soldering process according to claim 10, wherein the silver content is about 2.0 weight percent of the solder alloy, and the copper content is up to about 2.0 weight percent of the solder alloy. 14. A soldering process according to claim 10, wherein the indium content is about 53.5 to about 54.5 weight percent of the solder alloy.
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이 특허에 인용된 특허 (14)
Harada Masahide (Yokohamashi JPX) Ando Akihiro (Yokohama JPX) Satoh Ryohei (Yokohama JPX) Yabushita Akira (Yokohama JPX) Kanda Naoya (Yokosuka JPX) Horikoshi Kazuhiko (Kawasaki JPX), Circuit board with metal layer for solder bonding and electronic circuit device employing the same.
Mullen ; III William B. (Boca Raton FL) Banerji Kingshuk (Plantation FL) Bradley ; III Edwin L. (Sunrise FL) Kazem-Goudarzi Vahid (Sunrise FL), Multiple alloy solder preform.
Fister Julius C. (Hamden CT) Cherukuri Satyam C. (West Haven CT) Mahulikar Deepak (Meriden CT) O\Donnelly Brian E. (Branford CT), Semiconductor die attach system.
Kazem-Goudarzi Vahid (Sunrise FL) Bradley ; III Edwin L. (Sunrise FL) Banerji Kingshuk (Plantation FL) Liebman Henry F. (Tamarac FL), Solder clad substrate.
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