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An apparatus for testing the impedance of a medical lead connecting an implantable stimulation device to a nerve or a muscle. The implantable device is of the type comprising a capacitor for stimulating the nerve or the muscle. The system of the invention comprises a current generator for generating

An apparatus for testing the impedance of a medical lead connecting an implantable stimulation device to a nerve or a muscle. The implantable device is of the type comprising a capacitor for stimulating the nerve or the muscle. The system of the invention comprises a current generator for generating a testing current "I" during a calibrated testing pulse and a power circuit coupled to the capacitor and to the current generator for determining if the capacitor is charged by the testing current during the calibrated testing pulse.

대표청구항 ▼

1. An apparatus for testing the impedance of a medical lead connecting an implantable stimulation device to one of either a nerve or a muscle, the implantable device comprising capacitor for stimulating the nerve or the muscle, said apparatus comprising: a current generator for generating a testi

1. An apparatus for testing the impedance of a medical lead connecting an implantable stimulation device to one of either a nerve or a muscle, the implantable device comprising capacitor for stimulating the nerve or the muscle, said apparatus comprising: a current generator for generating a testing current `I` during a calibrated testing pulse `STI`, said current generator comprising a pulse generator for generating the calibrated testing pulse; and a power circuit coupled to the capacitor and to the current generator for determining if the capacitor is charged by the testing current during the calibrated testing pulse. 2. The apparatus of claim 1 wherein the current generator comprises at least one D/A converter (200). 3. The apparatus of claim 1 wherein the current generator is a low powered device operating in the range of five volts. 4. The apparatus of claim 1 wherein the current generator for generating a testing current "I" during a calibrated testing pulse "STI" is implemented within a low power ASIC. 5. The apparatus of claim 1 wherein the power circuit is a transistor device coupled to the output of the pulse generator. 6. The apparatus of claim 5 wherein the transistor device is a power transistor for adapting the low voltage calibrated testing pulse "STI" to the high power voltage of the capacitor. 7. The apparatus of claim 5 further comprising a measuring device connected to the output of the transistor device for measuring the transistor output voltage. 8. The apparatus of claim 7 wherein the measuring device comprises an A/D converter for converting the output voltage of the transistor device into binary bits. 9. The apparatus of claim 8 further comprising a register connected to the output of the A/D converter for storing the binary bits.