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Interconnections to copper IC's 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0546037 (2000-04-10)
발명자 / 주소
  • Moyer, Ralph Salvatore
  • Ryan, Vivian Wanda
출원인 / 주소
  • Agere Systems INC
대리인 / 주소
    Wilde, Peter V. D.
인용정보 피인용 횟수 : 42  인용 특허 : 7

초록 ▼

The specification describes a process for forming a barrier layer on copper metallization in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the ba

대표청구항 ▼

The specification describes a process for forming a barrier layer on copper metallization in semiconductor integrated circuits. The barrier layer is effective for both wire bond and solder bump interconnections. The barrier layer is Ti/Ni formed on the copper. Aluminum bond pads are formed on the ba

이 특허에 인용된 특허 (7)

  1. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
    상세보기
  2. Elenius Peter ; Hollack Harry, Method for forming chip scale package.
    상세보기
  3. Baker Mark H. (San Jose CA), Method for forming solder bumps in semiconductor devices.
    상세보기
  4. Higdon William David ; Stepniak Frank ; Yeh Shing, Method of solder bumping a circuit component.
    상세보기
  5. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
    상세보기
  6. Tsuchiya Yasuaki,JPX, Semiconductor device with a copper wiring pattern.
    상세보기
  7. DiGiacomo Giulio (Hopewell Junction NY) Kim Jung-Ihl (Seoul NY KRX) Narayan Chandrasekhar (Hopewell Junction NY) Purushothaman Sampath (Yorktown Heights NY), Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal.
    상세보기

이 특허를 인용한 특허 (42)

  1. Bhatt, Hemanshu; Vijay, Dilip; Pallinti, Jayanthi; Sun, Sey-Shing; Ying, Hong; Kao, Chiyi, Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.
    상세보기
  2. Craig,David M.; Chen,Chien Hua; Haluzak,Charles C.; Yenchik,Ronnie J., Assembly with a ring and bonding pads formed of a same material on a substrate.
    상세보기
  3. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.
    상세보기
  4. Fan, Yang-Tung; Chu, Cheng-Yu; Fan, Fu-Jier; Lin, Shih-Jane; Peng, Chiou-Shian; Chen, Yen-Ming; Lin, Kuo-Wei, Bumping process to increase bump height and to create a more robust bump structure.
    상세보기
  5. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
    상세보기
  6. Arvin, Charles L.; Gambino, Jeffrey P.; Musante, Charles F.; Muzzy, Christopher D.; Sauter, Wolfgang, Corrosion resistant aluminum bond pad structure.
    상세보기
  7. Arvin, Charles L.; Gambino, Jeffrey P.; Musante, Charles F.; Muzzy, Christopher D.; Sauter, Wolfgang, Corrosion resistant aluminum bond pad structure.
    상세보기
  8. Bojkov,Christo P.; Torres,Orlando F., Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion.
    상세보기
  9. Bojkov,Christo P.; Torres,Orlando F., Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion.
    상세보기
  10. Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
    상세보기
  11. Mis, J. Daniel; Engel, Kevin, Electronic devices including metallurgy structures for wire and solder bonding.
    상세보기
  12. Biggs,Julie C.; Cheng,Tien Jen; Eichstadt,David E.; Fanti,Lisa A.; Griffith,Jonathan H.; Knarr,Randolph F.; Knickerbocker,Sarah H.; Petrarca,Kevin S.; Quon,Roger A.; Sauter,Wolfgang; Srivastava,Kamal, I/C chip suitable for wire bonding.
    상세보기
  13. Ryan,Vivian, Integrated circuit having bond pad with improved thermal and mechanical properties.
    상세보기
  14. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.
    상세보기
  15. Lin,Yaojian; Do,Byung Tai; Looi,Wan Lay; Cao,Haijing, Integrated circuit system for bonding.
    상세보기
  16. Fogel, Keith E.; Ghosal, Balaram; Kang, Sung K.; Kilpatrick, Stephen; Lauro, Paul A.; Nye, III, Henry A.; Shih, Da-Yuan; Zupanski-Nielsen, Donna S., Interconnections for flip-chip using lead-free solders and having reaction barrier layers.
    상세보기
  17. Lee,Kong Weng; Ng,Kee Yean; Kuan,Yew Cheong; Tan,Gin Ghee; Tan,Cheng Why, Method for fabricating a packaging device for semiconductor die and semiconductor device incorporating same.
    상세보기
  18. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
    상세보기
  19. Hammer, Markus; Ruhl, Guenther; Strasser, Andreas; Melzl, Michael; Goellner, Reinhard; Groteloh, Doerthe, Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element.
    상세보기
  20. Hammer, Markus; Ruhl, Guenther; Strasser, Andreas; Melzl, Michael; Goellner, Reinhard; Groteloh, Doerthe, Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element.
    상세보기
  21. Pyo, Sung-Gyu; Kim, Dong-Joon, Package of MEMS device and method for fabricating the same.
    상세보기
  22. Lee,Kong Weng; Ng,Kee Yean; Kuan,Yew Cheong; Tan,Gin Ghee; Tan,Cheng Why, Packaging device for semiconductor die, semiconductor device incorporating same and method of making same.
    상세보기
  23. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
    상세보기
  24. Itou, Hiroyasu, Power composite integrated semiconductor device and manufacturing method thereof.
    상세보기
  25. Itou,Hiroyasu, Power composite integrated semiconductor device and manufacturing method thereof.
    상세보기
  26. Itou,Hiroyasu, Power composite integrated semiconductor device and manufacturing method thereof.
    상세보기
  27. Sun, Sey-Shing; Pallinti, Jayanthi; Vijay, Dilip; Bhatt, Hemanshu; Ying, Hong; Kao, Chiyi; Burke, Peter, Reduction of macro level stresses in copper/low-K wafers.
    상세보기
  28. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.
    상세보기
  29. Shinkai, Hiroyuki; Okumura, Hiroshi, Semiconductor device employing wafer level chip size package technology.
    상세보기
  30. Burrell, Lloyd G.; Wong, Kwong H.; Kelly, Adreanne A.; McKnight, Samuel R., Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad.
    상세보기
  31. Lee, Kong Weng; Ng, Kee Yean; Kuan, Yew Cheong; Tan, Cheng Why; Tan, Gin Ghee, Semiconductor device with a light emitting semiconductor die.
    상세보기
  32. Lindgren, Joseph T., Semiconductor device with copper wirebond sites and methods of making same.
    상세보기
  33. Lindgren, Joseph T., Semiconductor device with copper wirebond sites and methods of making same.
    상세보기
  34. Yahata, Kosuke; Goshonoo, Koichi; Moriyama, Miki, Semiconductor light emitting element.
    상세보기
  35. Bachman, Mark A.; Bitting, Donald S.; Chittipeddi, Sailesh; Kang, Seung H.; Merchant, Sailesh M., Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore.
    상세보기
  36. Takyu,Shinya; Iizuka,Kazuhiro; Kiritani,Mika, Stack MCP.
    상세보기
  37. Takyu, Shinya; Iizuka, Kazuhiro; Kiritani, Mika, Stack MCP and manufacturing method thereof.
    상세보기
  38. Takyu,Shinya; Iizuka,Kazuhiro; Kiritani,Mika, Stack MCP and manufacturing method thereof.
    상세보기
  39. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
    상세보기
  40. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
    상세보기
  41. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Wire and solder bond forming methods.
    상세보기
  42. Gleixner,Robert J.; Danielson,Donald; Paluda,Patrick M.; Naik,Rajan, Wirebond structure and method to connect to a microelectronic die.
    상세보기

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