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A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

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A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance. t gate insulating layer by using the floating gate insulating layer as a hard mask and removing a portion of the first conductive layer and the first insulating layer to expose the surface of the substrate, such that the remaining first conductive layer forms the floating gate and the remaining first insulating layer forms the first gate insulating layer; forming a second insulating layer on the surface of the substrate, the floating gate insulating layer, the floating gate and the first gate insulating layer; forming a second conductive layer on the second insulating layer; removing portions of the second conductive layer and the second insulating layer to form a second opening and a third opening, such that the remaining second conductive layer forms the control gate and the remaining second insulating layer forms the second gate insulating layer; forming a source region by implanting impurity ions through the second opening into the substrate; forming spacers on the sidewalls of the second opening and the third opening; and forming a drain regions on the substrate within the third opening. 2. The method as recited in claim 1, wherein the semiconductor substrate is a silicon substrate. 3. The method as recited in claim 1, wherein the first gate insulating layer is made of oxide formed by oxidation. 4. The method as recited in claim 1, wherein the first gate insulating layer has a thickness of 50 to 200 angstroms. 5. The method as recited in claim 1, wherein the first conductive layer is made of doped polycrystalline silicon. 6. The method as recited in claim 1, wherein the first conductive layer has a thickness of 100 to 2000 angstroms. 7. The method as recited in claim 1, wherein the barrier layer is made of oxide. 8. The method as recited in claim 1, wherein the barrier layer has a thickness of 500 to 2000 angstroms. 9. The method as recited in claim 1, wherein the angled implant is accomplished by implanting phosphorus, arsenic or argon. 10. The method as recited in claim 1, wherein the angled implant further comprises energy between 20 and 200 KeV. 11. The method as recited in claim 1, wherein the second insulating layer is made of oxide formed by chemical vapor deposition (CVD). 12. The method as recited in claim 1, wherein the second insulating layer has a thickness of 50 to 250 angstroms. 13. The method as recited in claim 1, wherein the second conductive layer is made of doped polycrystalline silicon. 14. The method as recited in claim 1, wherein the second conductive layer has a thickness of 1000 to 2000 angstroms. 15. A method of fabricating a flash memory cell, comprising the steps of: providing a semiconductor substrate; defining an active area on the substrate; forming a first gate insulating layer within the active area; forming a first conductive layer on the first gate insulating layer; forming a barrier layer on the first conductive layer; removing a portion of the barrier layer to form a first opening and expose a portion of the first conductive layer; performing an angled implant on the exposed surface of the first conductive layer to damage the crystalline structure of the surface of the first conductive layer. wherein the angle of implantation is less than 60 degrees relative to a normal to the first conductive layer; forming a floating gate insulating layer on the exposed surface of the first conductive layer by an oxidation process; removing the barrier layer; forming a floating gate and a first gate insulating layer by using the floating gate insulating layer as a hard mask and removing a portion of the first conductive layer and the first insulating layer to expose the surface of the substrate, such that the remaining first conductive layer forms the floating gate and the remaining first insulating layer forms the first gate insulating layer; forming a second insulating layer on the surface of the substrate, the floating gate insulating layer, the floating gate and the first gate insulating layer; forming a second conductive layer on the second insulating layer; removing portions of the second conductive layer and the second insulating layer to form a second opening and a third opening, such that the remaining second conductive layer forms the control gate and the remaining second insulating layer forms the second gate insulating layer; forming a source region by implanting impurity ions through the second opening into the substrate; forming spacers on the sidewalls of the second opening and the third opening; and forming a drain regions on the substrate within the third opening. 16. The method as recited in claim 15, wherein the first conductive layer is made of doped polycrystalline silicon. 17. The method as recited in claim 15, wherein the angled implant is accomplished by implanting phosphorus, arsenic or argon. 18. The method as recited in claim 15, wherein the angled implant further comprises energy between 20 and 200 KeV. d masks over the substrate to expose: the I/O area and the 1T RAM cell area not within the bit line contact junction; performing a second implantation; forming sidewall spacers so that the adjacent sidewall spacers between the respective pairs of capacitor plates and word lines being nearly merged; and performing a third implantation. 2. The method of claim 1, including the steps of: forming a first isolation structure within the substrate separating the core area from the 1T RAM cell area; and forming a second isolation structure within the substrate separating the 1T RAM cell area 14 from the I/O area. 3. The method of claim 1, including the steps of: forming an I/O N-well within the substrate within the I/O area; and forming a core N-well within the substrate within the core and 1T RAM cell areas. 4. The method of claim 1, including the step of: forming a triple gate oxide upon the substrate wherein the thinnest gate oxide layer is formed within the core area, the middle thickness gate oxide layer is formed within the 1T RAM cell area and the thickest gate oxide layer is formed within the I/O area. 5. The method of claim 1, including the step of: forming a triple gate oxide upon the substrate wherein the gate oxide layer formed within the core area has a thickness of less than about 20 .ANG., the middle thickness gate oxide layer formed within the 1T RAM cell area has a thickness of from about 20 to 32 .ANG. and the thickest gate oxide layer formed within the I/O area has a thickness of greater than about 32 .ANG.. 6. The method of claim 1, including the step of: forming a triple gate oxide upon the substrate wherein the gate oxide layer formed within the core area has a thickness of from about 15 to 20 .ANG., the middle thickness gate oxide layer formed within the 1T RAM cell area 14 has a thickness of from about 24 to 28 .ANG. and the thickest gate oxide layer formed within the I/O area has a thickness of from about 32 to 120 .ANG.. 7. The method of claim 1, including the step of: forming a triple gate oxide upon the substrate wherein the gate oxide layer formed within the core area has a thickness of from about 15 to 20 .ANG., the middle thickness gate oxide layer formed within the 1T RAM cell area 14 has a thickness of from about 24 to 28 .ANG. and the thickest gate oxide layer formed within the I/O area has a thickness of from about 50 to 70 .ANG.. 8. The method of claim 1, wherein the portions of the node junctions adjacent the word lines exposed by the core PLDD masks each have a width of from about 900 to 2000 .ANG.. 9. The method of claim 1, wherein the portions of the node junctions adjacent the word lines exposed by the core PLDD masks each have a width of from about 900 to 1500 .ANG.. 10. The method of claim 1, wherein the core and I/O LDD implants are each a P-type implant. 11. The method of claim 1, wherein the core LDD implant is conducted to a concentration of preferably from about 1×1014to 5×1014atoms/cm2and to a depth of from about 300 to 800 .ANG.. 12. The method of claim 1, wherein the core LDD implant is conducted to a concentration of preferably from about 2×1014to 4×1016atoms/cm2and to a depth of from about 400 to 600 .ANG.. 13. The method of claim 1, wherein the core LDD implant is conducted at an energy of from about 2 to 5 keV. 14. The method of claim 1, wherein the I/O LDD implant is conducted to a concentration of preferably from about 1×1013to 5×1013atoms/cm2and to a depth of from about 1000 to 3000 .ANG.. 15. The method of claim 1, wherein the I/O LDD implant is conducted to a concentration of preferably from about 2×1013to 4×1013atoms/cm2and to a depth of from about 2000 to 4000 .ANG.. 16. The method of claim 1, wherein the tilt pocket implant is conducted at an angle of from about 15 to 30° relative to the surface of