초록 ▼

A semiconductor device comprises a first plate-like base substrate having a substantially rectangular extrapolated outer shape in a plane parallel to the primary surface thereof, and the first plate-like base substrate has a base electrode on the rear surface thereof. A second plate-like base substr

A semiconductor device comprises a first plate-like base substrate having a substantially rectangular extrapolated outer shape in a plane parallel to the primary surface thereof, and the first plate-like base substrate has a base electrode on the rear surface thereof. A second plate-like base substrate is connected to the primary surface of the first plate-like base substrate, and the second plate-like base substrate has a substantially same extrapolated outer shape in a plane parallel to the primary surface of the first plate-like base substrate. The second plate-like base substrate has a penetrating hole perpendicular to the primary surface of the first plate-like base substrate. A plate-like cap member is connected to the second plate-like base substrate to cover the penetrating hole in the second plate-like base substrate. A semiconductor chip is housed in a cavity surrounded by the first plate-like base substrate, the second plate-like base substrate and the plate-like cap member, and the semiconductor chip is electrically connected to the base electrode. Further, the first and second plate-like base substrates are cut off at each ridge portion of the side surfaces thereof which correspond to a corner portion of the substantially rectangular extrapolated outer shape.

대표청구항 ▼

A semiconductor device comprises a first plate-like base substrate having a substantially rectangular extrapolated outer shape in a plane parallel to the primary surface thereof, and the first plate-like base substrate has a base electrode on the rear surface thereof. A second plate-like base substr

A semiconductor device comprises a first plate-like base substrate having a substantially rectangular extrapolated outer shape in a plane parallel to the primary surface thereof, and the first plate-like base substrate has a base electrode on the rear surface thereof. A second plate-like base substrate is connected to the primary surface of the first plate-like base substrate, and the second plate-like base substrate has a substantially same extrapolated outer shape in a plane parallel to the primary surface of the first plate-like base substrate. The second plate-like base substrate has a penetrating hole perpendicular to the primary surface of the first plate-like base substrate. A plate-like cap member is connected to the second plate-like base substrate to cover the penetrating hole in the second plate-like base substrate. A semiconductor chip is housed in a cavity surrounded by the first plate-like base substrate, the second plate-like base substrate and the plate-like cap member, and the semiconductor chip is electrically connected to the base electrode. Further, the first and second plate-like base substrates are cut off at each ridge portion of the side surfaces thereof which correspond to a corner portion of the substantially rectangular extrapolated outer shape. sured linewidth from a patterned mask layer target linewidth; etching, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer, wherein: in conjunction with the deviation of the patterned mask layer measured linewidth from the patterned mask layer target linewidth there is adjusted within the plasma etch method at least one plasma etch parameter such that a patterned target layer measured linewidth more closely approximates a patterned target layer target linewidth; and the measuring of the patterned mask layer measured linewidth while employing the optical diffraction method and the adjusting within the plasma etch method of the at least one plasma etch parameter are undertaken in-situ for each substrate within a series of substrates fabricated while employing the plasma etch method. 2. The method of claim 1 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications. 3. The method of claim 1 wherein the blanket target layer is formed from a material selected from the group consisting of conductor materials, semiconductor materials and dielectric materials. 4. The method of claim 1 wherein the blanket target layer is formed to a thickness of from about 1000 to about 4000 angstroms. 5. The method of claim 1 wherein the patterned mask layer is formed from a material selected from the group consisting of photoresist mask materials, hard mask materials and composites thereof.