초록 ▼

Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of suf

Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches. One embodiment of the invention allows for minimum supply voltages of 85 millivolts, an improvement of over nine hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts,

대표청구항 ▼

Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of suf

Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches. One embodiment of the invention allows for minimum supply voltages of 85 millivolts, an improvement of over nine hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts, t least one of said plurality of time shifted signals. 6. The method according to claim 5, wherein said storing step further comprises storing said value for said at least one of said plurality of time shifted signals on a first falling edge of said reference clock signal occurring subsequent to said first rising edge of said reference clock signal. 7. The method according to claim 6, wherein said sampling step further comprises sampling said at least one of said plurality of time shifted signals on a second rising edge of said reference clock signal occurring subsequent to said first rising edge of said reference clock signal, said sampling step yielding a second sampled value for said at least one of said plurality of time shifted signals. 8. The method according to claim 7, wherein said comparing step further comprises comparing said first and said second sampled value for said at least one of said plurality of time shifted signals. 9. An electronic circuit for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal, the electronic circuit comprising: means for generating a plurality of time shifted input clock signals, said time shifted signals shifted relative to the input clock signal; means for sampling said plurality of time shifted signals at periodic intervals relative to said reference clock signal; and means for comparing values for said sampled time shifted signals with values for the reference clock signal to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal, said variation selected from group consisting of said frequency of said input clock signal being less than said frequency of said reference clock signal, said frequency of said input clock signal being greater than said frequency of said reference clock signal, and said frequency of said input clock signal being equal to said frequency of said reference clock signal. 10. The electronic circuit according to claim 9, wherein said generating means further comprises means for shifting each of said plurality of time shifted signals by an amount equivalent to the period of said input clock signal divided by the number of said plurality of input clock signal. 11. The electronic circuit according to claim 10, wherein plurality of time shifted signals have the same frequency. 12. The electronic circuit according to claim 9, wherein said sampling means further comprises means for sampling at least one of said plurality of time shifted signals on a first rising edge of said reference clock signal, said sampling means yielding a first sampled value for said at least one of said plurality of time shifted signals. 13. The electronic circuit according to claim 12, wherein said sampling means further comprises means for storing a value for said at least one of said plurality of time shifted signals. 14. The electronic circuit according to claim 13, wherein said storing means further comprises means for storing said value for said at least one of said plurality of time shifted signals on a first falling edge of said reference clock signal occurring subsequent to said first rising edge of said reference clock signal. 15. The electronic circuit according to claim 14, wherein said sampling means further comprises means for sampling said at least one of said plurality of time shifted signals on a second rising edge of said reference clock signal occurring subsequent to said first rising edge of said reference clock signal, said sampling means yielding a second sampled value for said at least one of said plurality of time shifted signals. 16. The electronic circuit according to claim 15, wherein said comparing means further comprises means for comparing said first and said second sampled value for said at least one of said plurality of time shifted signals. 17. A high resolution frequency detection circuit for determining variance between an input cloc