초록 ▼

The assembly apparatus comprises a frame for supporting the straps of the first set of straps in mutually parallel positions, clamping and engagement for clamping on each of the straps of a second set of straps in succession and for engaging them with the straps of the first set in position in the s

The assembly apparatus comprises a frame for supporting the straps of the first set of straps in mutually parallel positions, clamping and engagement for clamping on each of the straps of a second set of straps in succession and for engaging them with the straps of the first set in position in the support frame, and at least one comb that is movable between a disengaged position and a position in which it engages each of the straps of the first set.

대표청구항 ▼

The assembly apparatus comprises a frame for supporting the straps of the first set of straps in mutually parallel positions, clamping and engagement for clamping on each of the straps of a second set of straps in succession and for engaging them with the straps of the first set in position in the s

The assembly apparatus comprises a frame for supporting the straps of the first set of straps in mutually parallel positions, clamping and engagement for clamping on each of the straps of a second set of straps in succession and for engaging them with the straps of the first set in position in the support frame, and at least one comb that is movable between a disengaged position and a position in which it engages each of the straps of the first set. 4; US-5161067, 19921100, Tomiyama et al., 360/044.15; US-5267089, 19931100, Yamamoto et al., 369/044.16; US-5313334, 19940500, Tomiyama et al., 369/044.16; US-5598397, 19970100, Sim, 369/044.15; US-5719834, 19980200, Futagawa et al., 369/044.15; US-5777972, 19980700, Furusawa, 369/044.14; US-5781352, 19980700, Ujiie et al., 369/044.14; US-5940357, 19990800, Yamamiya, 369/044.14 node and all the row address nodes are logically active. 6. The device of claim 1 wherein the logic gate of the first means comprises a plurality of series-connected transistors each having a gate, and each gate coupled to a different one of the row address nodes, the series-connected transistors forming a conducting path coupling the driver-gate node logically active when the section node and all the row address nodes are logically active. 7. The device of claim 1 wherein the turnoff device of the second means comprises a pullup transistor which, when activated in response to the section node being logically inactive, couples the driver-gate node logically inactive. 8. A method for copying data from row to row in a section of a memory array, the memory array being divided into sections, each section having an associated section node and a plurality of sense amplifiers, each section comprising a plurality of rows of memory cells, each row of memory cells being enabled for access by a dedicated wordline node being logically active, the wordline node being set logically active in response to the section node and a plurality of row address nodes all being logically active, the wordline node upon switching logically active being latched logically active during any subsequent changes in the row address nodes until the section node changes to a logically inactive value, the wordline node being set logically inactive when the section node is logically inactive, comprising the steps of: (a) setting the section node logically active such that at least one section of the memory is enabled for access, and retaining the section node logically active, while (b) enabling the sense amplifiers associated with the enabled section of the memory, and (c) within the enabled section of the memory, setting a plurality of row address nodes logically active such that an associated wordline node is set and latched logically active, thus enabling access to an associated row of memory cells, and (d) writing a plurality of data values to a plurality of chosen memory cells within the associated row of memory cells, one data value to each chosen memory cell, and (e) setting a plurality of predetermined new address values onto the row address nodes, one new address value after another, while keeping the sense amplifiers enabled, such that each of the new address values occurs once, each of the new address values being stabilized and retained substantially for sufficient time to set an associated new wordline node logically active to enable an associated new row of memory cells for access and to reliably write the associated new row of memory cells, previously enabled rows of memory cells within the section of the memory remaining enabled by the latching function of the current method while the row address values are changed, thus providing and propagating the data values to all chosen memory cells in each associated new row of memory cells simultaneously, thereby writing the data values to all predetermined rows of memory cells one after another essentially as rapidly as the set of new address values may be presented, and finally (f) setting the section node logically inactive, thus disabling further access to all rows of memory cells associated with the section node, thereby completing the operation of writing data values to chosen memory cells in predetermined rows of memory cells with a single enabling of the sense amplifiers for the enabled section of memory. 9. The method of claim 8, wherein at least one of the row address nodes is responsive to a control signal such that the row address node so regulated cannot be set logically active until both its row address signal and the control signal are logically active, the control signal thus regulating a time for enabling each wordline. 10. A device which implements the method of claim 8, for access of a row of memory cells within a section of a memory device, there being a plurality of rows of me