IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0086326
(2002-03-01)
|
발명자
/ 주소 |
- Fuller, Robert
- Davis, Chris
|
출원인 / 주소 |
- Prinzing Enterprises, Inc.
|
대리인 / 주소 |
McAndrews, Held & Malloy, Ltd.
|
인용정보 |
피인용 횟수 :
17 인용 특허 :
7 |
초록
▼
A valve lock for securing the handle of a pipe. The valve lock includes a first housing having first and second contact points for engaging the pipe and a retention chamber that receives the handle. The first housing is in a final position to prevent rotation of the handle when the retention chamber
A valve lock for securing the handle of a pipe. The valve lock includes a first housing having first and second contact points for engaging the pipe and a retention chamber that receives the handle. The first housing is in a final position to prevent rotation of the handle when the retention chamber receives the handle and the first and second contact points are seated against the pipe. A second housing has a third contact point for engaging the pipe and a lock member for disposition relative to the first housing when the first housing is in the final position and the third contact point is seated against the pipe. The lock member receives the shackle of a padlock to secure the lock member to the first housing.
대표청구항
▼
A valve lock for securing the handle of a pipe. The valve lock includes a first housing having first and second contact points for engaging the pipe and a retention chamber that receives the handle. The first housing is in a final position to prevent rotation of the handle when the retention chamber
A valve lock for securing the handle of a pipe. The valve lock includes a first housing having first and second contact points for engaging the pipe and a retention chamber that receives the handle. The first housing is in a final position to prevent rotation of the handle when the retention chamber receives the handle and the first and second contact points are seated against the pipe. A second housing has a third contact point for engaging the pipe and a lock member for disposition relative to the first housing when the first housing is in the final position and the third contact point is seated against the pipe. The lock member receives the shackle of a padlock to secure the lock member to the first housing. 438/149; US-5966193, 19991000, Zhang et al.; US-5982460, 19991100, Zhang et al.; US-5998841, 19991200, Suzawa; US-6004831, 19991200, Yamazaki et al.; US-6038006, 20000300, Sasaki et al.; US-6077731, 20000600, Yamazaki et al.; US-6114728, 20000900, Yamazaki et al.; US-6121652, 20000900, Suzawa; US-6124604, 20000900, Koyama et al., 257/059; US-6172671, 20010100, Shibuya et al., 257/059; US-6218219, 20010400, Yamazaki et al., 438/149; US-6338988, 20020100, Andry et al., 438/149; US-6403407, 20020600, Andry et al., 438/151; US-6407431, 20020600, Yamazaki et al., 257/353; US-6429058, 20020800, Colgan et al., 438/158 er the gate line and a data pad at the end of the data line; forming a first passivation layer to cover the data line, source and drain electrodes, the capacitor electrode and the data pad, the first passivation layer having a first drain contact hole to the drain electrode, a etching hole corresponding to a transmissive portion, a first capacitor contact hole to the capacitor electrode, a first gate pad contact hole to the gate pad, and a data pad contact hole to the data pad; forming a gate pad terminal, a data pad terminal and a transparent electrode in the transmissive portion, the gate pad terminal contacting the gate pad through the first gate pad contact hole, the data pad terminal contacting the data pad through the first data pad contact hole, and transparent electrode contacting the drain electrode and capacitor electrode through the first drain and capacitor contact holes; forming a second passivation layer to cover the transparent electrode, the gate pad terminal and the data pad terminal, the second passivation layer having a second drain contact hole over the drain electrode, a second capacitor contact hole over the capacitor electrode, a second gate pad contact hole over the gate pad, and a second data pad contact hole over the data pad; forming a corrosion-resistant metal layer on the second passivation layer; forming an aluminum-based layer on the corrosion-resistant metal layer; and patterning the aluminum-based layer and the corrosion-resistant metal layer so as to form a double-layered reflective electrode and expose the gate pad terminal and data pad terminal. 2. The method of claim 1, wherein the first layers of the gate line, gate electrode and gate pad are one of aluminum or aluminum neodymium. 3. The method of claim 1, wherein the second layers of the gate line, gate electrode and gate pad are titanium. 4. The method of claim 1, wherein the data line, source and drain electrodes, capacitor electrode and data pad are formed of chromium. 5. The method of claim 1, wherein the gate pad terminal, data pad terminal and transparent electrode are formed of a transparent conductive material selected from a group consisting of indium tin oxide, indium zinc oxide and indium tin zinc oxide. 6. The method of claim 1, wherein the corrosion-resistant metal is molybdenum. 7. The method of claim 1, wherein the aluminum-based layer is aluminum neodymium. 8. The method of claim 1, wherein the aluminum-based layer is pure aluminum. 9. A method of fabricating an array substrate for use in a transflective liquid crystal display device, the method comprising the steps of: forming a gate line, a gate electrode and a gate pad all having a single-layered structure on a substrate; forming a gate-insulating layer on the substrate to cover the gate line, the gate electrode and the gate pad; forming an active layer and an ohmic contact layer over the gate electrode; forming a data line, source and drain electrodes on the ohmic contact layer, a capacitor electrode over the gate line, and a data pad at the end of the data line, thereby defining intermediate structures; forming a first passivation layer to cover the intermediate structures, the first passivation layer having a first drain contact hole to the drain electrode, a etching hole corresponding to a transmissive portion, a first capacitor contact hole to the capacitor electrode, a gate pad contact hole to the gate pad, and a data pad contact hole to the data pad; forming a gate pad terminal, a data pad terminal and a transparent electrode in the transmissive portion, the gate pad terminal contacting the gate pad through the gate pad contact hole, the data pad terminal contacting the data pad through the first data pad contact hole, and transparent electrode contacting the drain electrode and capacitor electrode through the first drain and capacitor contact holes; forming a second passivation layer to cover the transparent electrode, the gate pad terminal and th
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