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Method and system for wafer level testing and burning-in semiconductor components 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/28
  • G01R-001/073
출원번호 US-0037562 (2002-01-07)
발명자 / 주소
  • Cram, Daniel P.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Gratton, Stephen A.
인용정보 피인용 횟수 : 139  인용 특허 : 26

초록

A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resil

대표청구항

A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resil

이 특허에 인용된 특허 (26)

  1. Farnworth Warren ; Wood Alan, Apparatus for manufacturing known good semiconductor dice.
  2. Agahdel Fariborz ; Griswold Brad ; Husain Syed ; Moti Robert ; Robinette ; Jr. William C. ; Ho Chung W., Bare die carrier.
  3. Ahmad Aftab (Boise ID) Weber Larren G. (Caldwell ID) Green Robert S. (Boise ID), Built-in test circuit connection for wafer level burnin and testing of individual dies.
  4. Tuckerman David (Dublin CA) Patel Pradip (Redwood City CA), Burn-in technologies for unpackaged integrated circuits.
  5. Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.
  6. Krug Heinz (c/o Akademie Meru ; Station 24 NL-6063 Vlodrop NLX), Circuit arrangement for testing integrated circuit components.
  7. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Component for connecting a semiconductor chip to a substrate.
  8. Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals.
  9. McClure David C. (Carrollton TX), Entire wafer stress test method for integrated memory devices and circuit therefor.
  10. Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
  11. Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX), Full wafer integrated circuit testing device.
  12. Wood Alan G. ; Farnworth Warren M. ; Akram Salman ; Hembree David R., Method and apparatus for testing unpackaged semiconductor dice.
  13. Daniel P. Cram, Method and system for wafer level testing and burning-in semiconductor components.
  14. Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
  15. DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX), Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located.
  16. Akram Salman ; Hembree David R. ; Wood Alan G., Method for testing semiconductor packages using decoupling capacitors to reduce noise.
  17. Khandros Igor Y. (Peekskil NY), Method of manufacturing electrical contacts, using a sacrificial member.
  18. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
  19. Whetsel Lee D., Process of testing integrated circuit dies on a wafer.
  20. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate.
  21. James Marc Leas ; Robert William Koss ; Jody John Van Horn ; George Frederick Walker ; Charles Hampton Perry ; David Lewis Gardell ; Steve Leo Dingle ; Ronald Prilik, Semiconductor wafer test and burn-in.
  22. Beffa Ray ; Nevill Leland R. ; Farnworth Warren M. ; Cloud Eugene H. ; Waller William K., System for stressing a memory integrated circuit die.
  23. Budnaitis John J. ; Leong Jimmy, Wafer level burn-in system.
  24. Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.
  25. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Wafer-level test and burn-in, and semiconductor process.
  26. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Wafer-scale techniques for fabrication of semiconductor chip assemblies.

이 특허를 인용한 특허 (139)

  1. Marokkey, Sajan; Sarma, Chandrasekhar; Gutmann, Alois, Alignment marks for polarized light lithography and method for use thereof.
  2. Cram,Daniel P., Apparatus for deforming resilient contact structures on semiconductor components.
  3. Caskey, Terrence; Mohammed, Ilyas; Uzoh, Cyprian Emeka; Woychik, Charles G.; Newman, Michael; Monadgemi, Pezhman; Co, Reynaldo; Chau, Ellis; Haba, Belgacem, BVA interposer.
  4. Subido, Willmar; Co, Reynaldo; Zohni, Wael; Prabhu, Ashok S., Ball bonding metal wire bond wires to metal pads.
  5. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  6. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  7. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  8. Katkar, Rajesh; Gao, Guilian; Woychik, Charles G.; Zohni, Wael, Bond via array for thermal conductivity.
  9. Kubota,Yoichi; Kang,Teck Gyu; Park,Jae M.; Haba,Belgacem, Components with posts and pads.
  10. Uzoh, Cyprian Emeka; Katkar, Rajesh, Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects.
  11. Dorough,Michael J.; Gravelle,Robert M.; Velichko,Sergey A., Dynamic creation and modification of wafer test maps during wafer testing.
  12. Dorough,Michael J.; Blunn,Robert G.; Velichko,Sergey A., Dynamically adaptable semiconductor parametric testing.
  13. Dorough,Michael J.; Blunn,Robert G.; Velichko,Sergey A., Dynamically adaptable semiconductor parametric testing.
  14. Dorough,Michael J.; Blunn,Robert G.; Velichko,Sergey A., Dynamically adaptable semiconductor parametric testing.
  15. Dorough,Michael J.; Blunn,Robert G.; Velichko,Sergey A., Dynamically adaptable semiconductor parametric testing.
  16. DeLaCruz, Javier A.; Awujoola, Abiola; Prabhu, Ashok S.; Lattin, Christopher W.; Sun, Zhuowen, Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces.
  17. Haba, Belgacem; Mohammed, Ilyas, Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.
  18. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.
  19. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.
  20. Haba, Belgacem; Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M., Fine pitch microcontacts and method for forming thereof.
  21. Kwon, Jinsu, Flip chip interconnection with double post.
  22. Haba, Belgacem; Beroz, Masud; Kim, Young-Gon; Tuckerman, David B., Formation of circuitry with modification of feature height.
  23. Haba,Belgacem; Beroz,Masud; Kim,Young Gon; Tuckerman,David B., Formation of circuitry with modification of feature height.
  24. Mohammed, Ilyas; Beroz, Masud, Heat spreading substrate with embedded interconnects.
  25. Velichko,Sergey A.; Dorough,Michael J.; Blunn,Robert G., Intelligent measurement modular semiconductor parametric test system.
  26. Gupta, Debabrata; Hashimoto, Yukio; Mohammed, Ilyas; Mirkarimi, Laura Wills; Katkar, Rajesh, Interconnect structure.
  27. Gupta, Debabrata; Hashimoto, Yukio; Mohammed, Ilyas; Mirkarimi, Laura; Katkar, Rajesh, Interconnect structure.
  28. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.
  29. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.
  30. Kirby,Kyle K.; Farnworth,Warren M., Method for fabricating a semiconductor interconnect having conductive spring contacts.
  31. Kirby,Kyle K.; Farnworth,Warren M., Method for fabricating semiconductor components with conductive spring contacts.
  32. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Method for making a microelectronic assembly having conductive elements.
  33. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.
  34. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.
  35. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  36. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  37. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  38. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  39. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  40. Fjelstad, Joseph, Method of electrically connecting a microelectronic component.
  41. Zhao, Zhijun; Alatorre, Roseann, Method of forming a component having wire bonds and a stiffening layer.
  42. Mohammed, Ilyas, Method of forming a wire bond having a free end.
  43. Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M.; Haba, Belgacem, Method of making a connection component with posts and pads.
  44. Kubota, Yoichi; Kang, Teck-Gyu; Park, Jae M.; Haba, Belgacem, Method of making a connection component with posts and pads.
  45. Kreager,Douglas P., Methods and apparatus for testing circuit boards.
  46. Fjelstad, Joseph; Karavakis, Konstantine, Methods of making compliant semiconductor chip packages.
  47. Kovac,Zlata; Mitchell,Craig S.; DiStefano,Thomas H.; Smith,John W., Methods of making microelectronic assemblies including compliant interfaces.
  48. Damberg, Philip; Haba, Belgacem; Tuckerman, David B.; Kang, Teck-Gyu, Micro pin grid array with pin motion isolation.
  49. Damberg, Philip; Haba, Belgacem; Tuckerman, David B.; Kang, Teck-Gyu, Micro pin grid array with pin motion isolation.
  50. Haba, Belgacem; Beroz, Masud; Kang, Teck-Gyu; Kubota, Yoichi; Krishnan, Sridhar; Riley, III, John B.; Mohammed, Ilyas, Microelectonic packages and methods therefor.
  51. Haba, Belgacem, Microelectronic assemblies having compliancy.
  52. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  53. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  54. Oganesian, Vage; Gao, Guilian; Haba, Belgacem; Ovrutsky, David, Microelectronic assemblies having compliancy and methods therefor.
  55. Fjelstad,Joseph; Karavakis,Konstantine, Microelectronic assemblies having compliant layers.
  56. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation.
  57. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.
  58. Haba, Belgacem; Mitchell, Craig S., Microelectronic assemblies having very fine pitch stacking.
  59. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation.
  60. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface.
  61. Humpston,Giles; Thompson,Jesse Burl, Microelectronic component with foam-metal posts.
  62. Haba, Belgacem; Crisp, Richard Dewitt; Zohni, Wael, Microelectronic element with bond elements to encapsulation surface.
  63. Haba, Belgacem; Beroz, Masud; Humpston, Giles; Park, Jae M., Microelectronic package comprising offset conductive posts on compliant layer.
  64. Prabhu, Ashok S.; Katkar, Rajesh, Microelectronic package for wafer-level chip scale packaging with fan-out.
  65. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  66. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  67. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  68. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  69. Haba, Belgacem; Beroz, Masud; Green, Ronald; Mohammed, Ilyas; Wilson, Stuart E.; Zohni, Wael; Kubota, Yoichi; Thompson, Jesse Burl, Microelectronic packages and methods therefor.
  70. Haba, Belgacem; Beroz, Masud; Kang, Teck-Gyu; Kubota, Yoichi; Krishnan, Sridhar; Riley, III, John B.; Mohammed, Ilyas, Microelectronic packages and methods therefor.
  71. Haba, Belgacem; Beroz, Masud; Kang, Teck-Gyu; Kubota, Yoichi; Krishnan, Sridhar; Riley, III, John B.; Mohammed, Ilyas, Microelectronic packages and methods therefor.
  72. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  73. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  74. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  75. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  76. Haba,Belgacem; Beroz,Masud; Green,Ronald; Mohammed,Ilyas; Wilson,Stuart E.; Zohni,Wael; Kubota,Yoichi; Thompson,Jesse Burl, Microelectronic packages and methods therefor.
  77. Humpston, Giles; Gao, Guilian; Haba, Belgacem, Microelectronic packages and methods therefor.
  78. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.
  79. Haba, Belgacem, Microelectronic packages with dual or multiple-etched flip-chip connectors.
  80. Haba, Belgacem, Microelectronic packages with nanoparticle joining.
  81. Haba, Belgacem, Microelectronic packages with nanoparticle joining.
  82. Haba, Belgacem, Microelectronic packages with nanoparticle joining.
  83. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.
  84. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.
  85. Haba, Belgacem; Co, Reynaldo; Cizek, Rizza Lee Saga; Zohni, Wael, Off substrate kinking of bond wire.
  86. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Off substrate kinking of bond wire.
  87. Fliegner, Jens; Ebert, Andreas, Operating device for a motor vehicle.
  88. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  89. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  90. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  91. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  92. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  93. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young; Zhao, Zhijun, Package-on-package assembly with wire bond vias.
  94. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  95. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  96. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  97. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  98. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  99. Prabhu, Ashok S.; Katkar, Rajesh, Packaged microelectronic device for a package-on-package device.
  100. Haba, Belgacem; Mohammed, Ilyas, Pin attachment.
  101. Co, Reynaldo; Villavicencio, Grant; Zohni, Wael, Pressing of wire bond wire tips to provide bent-over tips.
  102. Mohammed, Ilyas, Reconstituted wafer-level package DRAM.
  103. Mohammed, Ilyas, Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package.
  104. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  105. Kang, Teck-Gyu; Wang, Wei-Shun; Sato, Hiroaki; Hashimoto, Kiyoaki; Nakadaira, Yoshikuni; Masuda, Norihito; Haba, Belgacem; Mohammed, Ilyas; Damberg, Philip, Semiconductor chip assembly and method for making same.
  106. Kirby,Kyle K.; Farnworth,Warren M., Semiconductor interconnect having compliant conductive contacts.
  107. Kirby,Kyle K.; Farnworth,Warren M., Semiconductor interconnect having conductive spring contacts.
  108. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Severing bond wire by kinking and twisting.
  109. Wilson, Stuart E.; Green, Ronald; Crisp, Richard Dewitt; Humpston, Giles, Stack microelectronic assemblies.
  110. Haba, Belgacem, Stackable molded microelectronic packages.
  111. Haba, Belgacem, Stackable molded microelectronic packages.
  112. Haba, Belgacem, Stackable molded microelectronic packages.
  113. Haba, Belgacem, Stackable molded microelectronic packages.
  114. Haba, Belgacem, Stackable molded microelectronic packages.
  115. Haba, Belgacem, Stackable molded microelectronic packages with area array unit connectors.
  116. Haba, Belgacem, Stackable molded microelectronic packages with area array unit connectors.
  117. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  118. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  119. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  120. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  121. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  122. Villavicencio, Grant; Lee, Sangil; Alatorre, Roseann; Delacruz, Javier A.; McGrath, Scott, Stiffened wires for offset BVA.
  123. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.
  124. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.
  125. Haba, Belgacem; Mohammed, Ilyas, Structure for microelectronic packaging with terminals on dielectric mass.
  126. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.
  127. Uzoh, Cyprian Emeka, Structures and methods for low temperature bonding using nanoparticles.
  128. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  129. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  130. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  131. Kirby,Kyle K.; Farnworth,Warren M., Test system for semiconductor components having conductive spring contacts.
  132. McElrea, Simon; Zohni, Wael; Haba, Belgacem, Through interposer wire bond using low CTE interposer with coarse slot apertures.
  133. Katkar, Rajesh; Vu, Tu Tam; Lee, Bongsub; Bang, Kyong-Mo; Li, Xuan; Huynh, Long; Guevara, Gabriel Z.; Agrawal, Akash; Subido, Willmar; Mirkarimi, Laura Wills, Wafer-level packaging using wire bond wires in place of a redistribution layer.
  134. Co, Reynaldo; Zohni, Wael; Cizek, Rizza Lee Saga; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.
  135. Co, Reynaldo; Zohni, Wael; Saga Cizek, Rizza Lee; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.
  136. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.
  137. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.
  138. Huang, Shaowu; Delacruz, Javier A., Wire bonding method and apparatus for electromagnetic interference shielding.
  139. Prabhu, Ashok S.; Katkar, Rajesh, ‘RDL-First’ packaged microelectronic device for a package-on-package device.
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