초록 ▼

A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is con

A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

대표청구항 ▼

A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is con

A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage. e, wherein the at least one pad comprises reference and test pads. 7. The circuit of claim 6 wherein the first and third switches comprise P-Field Effect Transistors (FETs), wherein the second and fourth switches comprise N-FETs. 8. The circuit of claim 6 wherein the reference capacitive structure comprises a top plate comprising at least one first integrated circuit structure and a bottom plate comprising at least one second integrated circuit structure, and wherein the test capacitive structure comprises a top plate comprising at least one third integrated circuit structure and a bottom plate comprising at least one fourth integrated circuit structure. 9. The circuit of claim 6 wherein when the first and third switches are active, the second and fourth switches are inactive. 10. The circuit of claim 9 wherein the clock circuit comprises a ring oscillator, a delay, an AND gate and an OR gate, the ring oscillator having an output, the output coupled to the delay, coupled to an input to the OR gate, and coupled to an input to the AND gate, an output of the delay coupled to a second input of the OR gate and a second input of the AND gate, wherein the first clock signal is an output of the OR gate