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A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data

A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

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1. A method of synchronizing the generation and consumption of isochronous data in a computer system, comprising: providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data; outputting a master clock signal to the plurali

1. A method of synchronizing the generation and consumption of isochronous data in a computer system, comprising: providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data; outputting a master clock signal to the plurality of isochronous sinks or sources; synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal; outputting said master clock signal to an interrupt controller; and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. 2. The method of claim 1 wherein said clocks are synchronized to a multiple of said master clock signal. 3. A computer system comprising: a processor; a plurality of isochronous data sinks or sources configured to consume or generate isochronous data, wherein the plurality of isochronous data sinks or sources comprises a plurality of tasks that generate or consume isochronous data, wherein the processor is configured to schedule the plurality of tasks; and a clock controller configured to generate a master clock signal, wherein the consumption or generation of isochronous data by the isochronous data sinks or sources is synchronized to the master clock signal. 4. The computer system of claim 3, further comprising an interrupt controller, wherein the clock controller is configured to provide the master clock signal to the interrupt controller, wherein the interrupt controller is configured to generate an interrupt to the processor so that the generation or consumption of isochronous data by the plurality of tasks is synchronized to the master clock signal. 5. The computer system of claim 4, wherein the interrupt controller is further configured to divide the master clock signal. 6. The computer system of claim 3, further comprising a system clock configured to clock the processor by generating a system clock signal, wherein the master clock signal is derived from the system clock signal. 7. The computer system of claim 3, wherein the clock controller is configured to derive the master clock signal from a frame clock of one of the isochronous data sinks or sources. 8. The computer system of claim 3, wherein the clock controller is configured to derive the master clock signal from a data rate at which one of the isochronous data sinks or sources is generating or consuming isochronous data. 9. The computer system of claim 8, wherein the clock controller is further configured to adjust the master clock signal in response to a lead or a lag between the master clock signal and a clock of one of the isochronous data sinks or sources. 10. The computer system of claim 3, wherein one of the isochronous data sources or sinks is configured to synchronize a clock of the isochronous data source or sink to the master clock signal in response to a drift of the clock of the isochronous data source or sink relative to the master clock signal. 11. The computer system of claim 10, further comprising a data buffer configured to buffer isochronous data transfers, wherein the drift is measured by a level of isochronous data in the data buffer. 12. The computer system of claim 3, wherein the clock controller is configured to generate a plurality of clock signals from the master clock signal and to provide the plurality of clock signals to the plurality of isochronous data sources or sinks. 13. The computer system of claim 3, further comprising a signal processor configured to synchronize the generation or consumption of isochronous data by one or more of the isochronous data sources or sinks to the master clock signal by interpolating the isochronous data being generated or consumed. 14. The computer system of claim 3, wherein a rate of the master clock signal is controlled by software.