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A training kit is designed for use with a firearm normally having a standard bolt that is provided at the forward end with a bolt recess for receiving and embracing the head end of a standard cartridge. The training kit is provided with a training bolt having a circular recess of a diameter that wil

A training kit is designed for use with a firearm normally having a standard bolt that is provided at the forward end with a bolt recess for receiving and embracing the head end of a standard cartridge. The training kit is provided with a training bolt having a circular recess of a diameter that will not receive and embrace the head end of the standard cartridge thereby limiting placement of a standard cartridge beyond the reach of the firing pin. Rounds of reduced-energy training ammunition are provided with a head end of complementary dimensions that permits the head end to be seated within the recess of a conversion bolt, and therefore fired.

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A training kit is designed for use with a firearm normally having a standard bolt that is provided at the forward end with a bolt recess for receiving and embracing the head end of a standard cartridge. The training kit is provided with a training bolt having a circular recess of a diameter that wil

A training kit is designed for use with a firearm normally having a standard bolt that is provided at the forward end with a bolt recess for receiving and embracing the head end of a standard cartridge. The training kit is provided with a training bolt having a circular recess of a diameter that will not receive and embrace the head end of the standard cartridge thereby limiting placement of a standard cartridge beyond the reach of the firing pin. Rounds of reduced-energy training ammunition are provided with a head end of complementary dimensions that permits the head end to be seated within the recess of a conversion bolt, and therefore fired. of designating an input sequence for said path, said input sequence corresponding to a sequence of input values associated with said series of state transitions and collectively comprising an input signature. 9. The method of claim 8, further comprising the step of laying out said finite state machine in a physical circuit design. 10. The method of claim 9, further comprising the step of applying said input sequence to a portion of said physical circuit design corresponding to said finite state machine, and detecting a test output sequence therefrom. 11. The method of claim 10, further comprising the step of comparing said test output sequence to said output signature. 12. The method of claim 11, further comprising the step of obtaining said output signature from a database of I/C signatures. 13. The method of claim 12, wherein said step of obtaining said output signature from said database of I/O signatures comprises the step of connecting said database over a wide area network, issuing a query to an application server connected to said database, and receiving a message from said application server over said wide area network, said message comprising an indication of whether said test output sequence exists in said database of I/O signatures. 14. A method for watermarking a circuit design, said circuit design comprising at least one internal sequential function, said method comprising the steps of: identifying free input configurations in an internal sequential function of the circuit design, each free input configuration being without a specified output or destination state; and modifying said internal sequential function of the circuit design to generate a predictable output sequence when a specified input sequence is applied, by using said free input configurations. 15. The method of claim 14, wherein said circuit design is functionally complete prior to said step of identifying free input configurations and said step of modifying said internal sequential function of the circuit design. 16. The method of claim 14, wherein said output sequence is unrelated to the functionality of the circuit design. 17. The method of claim 14, further comprising the step of summing said free input configurations, testing the sum of said free input configurations against at least one watermarking robustness criterion, and adding additional free input configurations if said at least one watermarking robustness criterion is not met. 18. The method of claim 17, wherein said internal sequential function is embodied in a finite state machine, and wherein said step of adding additional free input configurations comprises the step of adding an input, an output or an additional state to said finite state machine. 19. The method of claim 18, further comprising the step of selecting an output sequence according in part to a random key. 20. The method of claim 18, wherein said step of modifying said internal sequential function of the circuit design comprises the step of selecting a path among said free input configurations, assigning output values to state transitions along said path to define said predictable output sequence. 21. The method of claim 20, wherein input values along said path among said free input configurations collectively define said specified input sequence. 22. The method of claim 20, wherein said step of selecting said path among said free input configurations comprises the step of searching a decision tree for an optimal path, said decision tree comprising an initial state at its root and subsequent states at its leaves. 23. The method of claim 20, wherein said step of selecting said path among said free input configurations comprises the step of using a Monte Carlo analysis to select the free input configurations for said path. 24. The method of claim 20, wherein said step of selecting said path among said free input configurations comprises the steps of randomly selecting a set of input