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A thrust reverser system for a jet engine has a thrust reverser sleeve lock, preferably for each thrust reverser sleeve, that provides at least one of the redundant anti-deployment mechanisms of the thrust reverser. The thrust reverser sleeve lock has a lock pin that engages a thrust reverser sleeve

A thrust reverser system for a jet engine has a thrust reverser sleeve lock, preferably for each thrust reverser sleeve, that provides at least one of the redundant anti-deployment mechanisms of the thrust reverser. The thrust reverser sleeve lock has a lock pin that engages a thrust reverser sleeve when the thrust reverser sleeve is in a stowed position and the thrust reverser sleeve lock is in a lock position to prevent the thrust reverser sleeve from deploying. In an embodiment of the invention, the thrust reverser sleeve lock includes an single-action hydraulically actuated actutor to which the lock pin is affixed, the actuator extending the lock pin through a lock hole in the thrust reverser sleeve when the thrust reverser sleeve is in its stowed position and the thrust reverser sleeve lock is in a lock position.

대표청구항 ▼

A thrust reverser system for a jet engine has a thrust reverser sleeve lock, preferably for each thrust reverser sleeve, that provides at least one of the redundant anti-deployment mechanisms of the thrust reverser. The thrust reverser sleeve lock has a lock pin that engages a thrust reverser sleeve

A thrust reverser system for a jet engine has a thrust reverser sleeve lock, preferably for each thrust reverser sleeve, that provides at least one of the redundant anti-deployment mechanisms of the thrust reverser. The thrust reverser sleeve lock has a lock pin that engages a thrust reverser sleeve when the thrust reverser sleeve is in a stowed position and the thrust reverser sleeve lock is in a lock position to prevent the thrust reverser sleeve from deploying. In an embodiment of the invention, the thrust reverser sleeve lock includes an single-action hydraulically actuated actutor to which the lock pin is affixed, the actuator extending the lock pin through a lock hole in the thrust reverser sleeve when the thrust reverser sleeve is in its stowed position and the thrust reverser sleeve lock is in a lock position. specified finite sequential machines", Mar. 1990. IEEE, pp. 552-556.* Kirovski, "Intellectual property protection by watermarking combinational logic synthesis solutions", Nov. 1998. IEEE, pp. 194-198.* Naik, "Efficient computation of unique I/O sequences in FSM's", Aug. 1997. IEEE, pp. 585-599.* Oikonomou, "Abstractions of finite-state machines and optimality with respect to immediately-detectable next-state faults", Jan. 1996. IEEE, pp. 151-160.* Lach, "Robust FPGA intellectual property protection through multiple samll watermarks", Jun. 1999. IEEE, pp. 831-836.* Kahng, "Watermarking techniques for intellectual property protection", Jun. 1998. IEEE, pp. 776-781.* Lach, "Signature hiding techniques for FPGA intellectual property protection", Nov. 1998. IEEE, pp. 186-189. Sentovich, "Sequential circuit design using synthesis and optimazation", Oct. 1992. IEEE, pp. 328-333. Pfleeger, "state reduction of completely specified FSM's", 1973. IEEE, pp. 1099-1102. Demir, Alper, et al., "Modeling and Simulation of the Interference due to Digital Switching in Mixed-Signal ICs," 1999 IEEE/ACM International Conference on Computer-Aided Design, Nov. 7-11, 1999, pp. 70-74. Charbon, E., "Hierarchical Watermarking in IC Design," Proc. IEEE Custom Integrated Circuits Conference, May 1998, pp. 295-298. Charbon, E., et al., "Watermarking Layout Topologies," IEEE Asia-South Pacific Design Automation Conference, May 1999, pp. 213-216. Torunoglu, I., et al, "Watermarking-Based Copyright Protection of Sequential Functions." Swanson, et al., "Transparent Robust Image Watermarking", in Proc, IEEE International Conference in Image Processing, vol. 3, pp. 211-214, Sep. 1996. Boney, et al., "Digital Watermarks for Audio Signals", in Proc. IEEE International Conference on Multimedia Computing and Systems, pp. 473-480, Jun. 1996. Lach, et al., "FPGA Fingerprinting Techniques for Protecting Intellectual Property". In Proc. IEEE Custom Integrated Circuit Conference, pp. 299-302, May 1998. Kahng, et al., "Robust IP Watermarking Methodologies for Physical Design" in Proc. IEEE/ACM Design Automation Conference. pp. 782-787, Jun. 1998. Villa, et al., "Synthesis of Finite State Machines: Logic Optimization, " Chapter 5 -Symbolic Minimization; Kluwer Academic Publ., Boston, MA 1997. De. Micheli, "Synthesis and Optimization of Digital Circuits". Chapter 9 -Sequential Logic Optimization-McGraw-Hill, 1994.