초록 ▼

Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (1810) is sensed by sensors (1820) that output electrical signals in response to the analyte. The electrical signals are preprocessed (1830) by filtering and a

Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (1810) is sensed by sensors (1820) that output electrical signals in response to the analyte. The electrical signals are preprocessed (1830) by filtering and amplification. In an embodiment, this preprocessing includes adapting the sensor and electronics to the environment in which the analyte exists. The electrical signals are further processed (1840) to classify and identify the analyte, which may be by a neural network.

대표청구항 ▼

1. A circuit for an analyte detection system comprising: a sensor site wherein sensor material is constrained at the sensor site and has regions of a nonconductive organic material and a conductive material, and in the presence of an analyte, the sensor material has a measurable change in an elec

1. A circuit for an analyte detection system comprising: a sensor site wherein sensor material is constrained at the sensor site and has regions of a nonconductive organic material and a conductive material, and in the presence of an analyte, the sensor material has a measurable change in an electrical property; and a floating gate device coupled to the sensor site, wherein the floating gate device stores an analog value, representative of the measurable chance in the electrical property from the sensor site, based on an amount of charge on a floating gate of the floating gate device; and the analog value is used by the analog detection system to determine the presence of the analyte. 2. The circuit of claim 1 further comprising: a first transistor coupled between a first supply voltage and a first node, wherein a gate of the first transistor is coupled to the floating gate device; and a second transistor coupled between the first node and a second supply voltage, wherein a gate of the second transistor is coupled to a bias voltage. 3. The circuit of claim 2 wherein the first transistor is a PMOS device and the second transistor is an NMOS device. 4. The circuit of claim 2 further comprising: a capacitor coupled between the first node and the floating gate device. 5. The circuit of claim 1 wherein the floating gate device stores an analog value with about 14 bits or greater of accuracy. 6. The circuit of claim 1 wherein the floating gate device stores an analog value having 14 bits or less of accuracy. 7. The circuit of claim 1 wherein the floating gate device provides nonvolatile storage. 8. The circuit of claim 1 wherein the floating gate device operates in the subthreshold regime.