Ceramic semiconductor package and method for fabricating the package
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-023/04
H01L-023/12
H03H-011/00
H03H-009/02
출원번호
US-0881343
(2001-06-13)
발명자
/ 주소
Glenn, Thomas P.
Hollaway, Roy D.
Webster, Steven
출원인 / 주소
Amkor Technology, Inc.
대리인 / 주소
Bever, Hoffman & Harms, LLP
인용정보
피인용 횟수 :
15인용 특허 :
22
초록▼
A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected th
A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate.
대표청구항▼
A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected th
A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate. he core material. 7. The substrate according to claim 6, further comprising through holes formed to interconnect the first and second surfaces of the core material, wherein inner surfaces of the holes are covered with conductive layers, and wherein the conductive layers are electrically connected to the respective inner wiring lines. 8. The substrate according to claim 6, wherein the combination of the mounting area of the core material, the inner terminals, the external terminals, and the inner wiring lines constitute a device formation assembly, and wherein the substrate further comprises an additional device formation assembly on the core material, the additional device assembly having the same configuration as the device formation assembly and being located at a specific interval from the device assembly. 9. A substrate for a semiconductor device, comprising: a dielectric core material with a first surface and a second surface, the core material having mounting areas on the first surface for mounting respective semiconductor elements on he first surface, the core material having a contact area; sets of inner terminal formed on the first surface of the core material at the respective mounting are s for electrical connection to a semiconductor element mounted on one of the mounting areas of the core material; sets of external terminals formed on the second surface of the core material for electrical connection to an external circuit provided outside the substrate; sets of inner wiring un s formed on the core material, each of the sets of inner wiring lines connecting electrically one of the sets of inner terminals with a corresponding one of the set of external terminals, at least one of each of the sets of inner wiring lines extending to the contact area of the core material in such a way as to be able to contact an external conductor provided outside the substrate; and a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is formed to over the first surface of the core material except for the mounting areas, the sets of contact areas, and the sets of inner terminals, and wherein the second dielectric layer is formed to cover the second surface of the core material except for the sets of external terminals, wherein each of the mounting areas of the core material, a corresponding one of the sets of inner terminals, a corresponding one of the sets of external terminals, and a corresponding one of the sets of inner wiring lines constitute a device formation assembly. 10. The substrate according to claim 9, wherein each of the first and second dielectric layers is a solder resist layer. 11. The substrate according to claim 9, wherein the sets of inner wiring lines located in the contact area are not electrically short-circuited with each other. 12. The substrate according to claim 9, wherein the contact area is located on at least one of the first surface of the core material and the second surface thereof. 13. The substrate according to claim 12, wherein the contact area is located near an edge of the ore material. 14. The substrate according to claim 9, wherein the contact area is located on a side of the core material that interconnects the first and second surfaces of the core material. 15. The substrate according to claim 14, further comprising through holes formed to interconnect the first and second surfaces of the core material, wherein inner surfaces of the holes are covered with conductive layers, and wherein the conductive layers are electrically connected to the respective sets of inner wiring lines. 16. The substrate according to claim 9, wherein the device formation assemblies are arranged at regular intervals along an axis of the core material, and wherein the contact area is shared by all the device formation assemblies.
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이 특허에 인용된 특허 (22)
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