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A system for implanting a wire antenna in a contactless smart card includes an ultrasonic implanting head with a voice-coil actuator to control the pressure at which a heated wire is forced into a plastic card substrate. The force produced by the actuator is proportional to the current in a coil win

A system for implanting a wire antenna in a contactless smart card includes an ultrasonic implanting head with a voice-coil actuator to control the pressure at which a heated wire is forced into a plastic card substrate. The force produced by the actuator is proportional to the current in a coil winding in the actuator. A controller uses a feedback system to maintain a relatively constant applied pressure. The feedback system monitors the current in the coil and the controller issues electronic signals to increase or decrease the current in the coil in response to the monitored current.

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A system for implanting a wire antenna in a contactless smart card includes an ultrasonic implanting head with a voice-coil actuator to control the pressure at which a heated wire is forced into a plastic card substrate. The force produced by the actuator is proportional to the current in a coil win

A system for implanting a wire antenna in a contactless smart card includes an ultrasonic implanting head with a voice-coil actuator to control the pressure at which a heated wire is forced into a plastic card substrate. The force produced by the actuator is proportional to the current in a coil winding in the actuator. A controller uses a feedback system to maintain a relatively constant applied pressure. The feedback system monitors the current in the coil and the controller issues electronic signals to increase or decrease the current in the coil in response to the monitored current. 0 MS/s 3 V Supply CMOS A/D Converter," IEEE Journal of Solid-State Circuits, IEEE, vol. 29, No. 12, Dec. 994, pp. 1531-1536. Kattman, K. and Barrow, J., "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters," IEEE International Solid-State Conference, IEEE, 1991, pp. 170-171. Kusumoto, K. et al., "A 10-b 20-MHz 30-mW Pieplined Interpolating CMOS ADC," IEEE Journal of Solid-State Circuits, IEEE, vol. 28, No. 12, Dec. 1993, pp. 1200-1206. Lewis, S. et al., "A 10-b 20-Msample/s Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, IEEE, vol. 27, No. 3, Mar. 1992, pp. 351-358. Mehr, I. and Singer, L., "A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC," IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 3, Mar. 2000, pp. 318-325. Nagaraj, K. et al., "Efficient 6-Bit A/D Converter Using a 1-Bit Folding Front End," IEEE Journal of Solid-State Circuits, IEEE, vol. 34, No. 8, Aug. 1999, pp. 1056-1062. Nagaraj, K. et al., "A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25-μm Digital CMOS," IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 12, Dec. 2000, pp. 1760-1768. Nauta, B. and Venes, A., "A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter," IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 12, Dec. 1995, pp. 1302-1308. Pan, H. et al., "A 3.3-V 12-b 50-MS/s A/D Converter in 0.6- μm CMOS with over 80-dB SFDR," IEEE Journal of Solid-State Circuits, IEEE, vol. 35, No. 12, Dec. 2000, pp. 1769-1780. Song, W-C. et al., "A 10-b 20-Msample/s Low-Power Cmos ADC," IEEE Journal of Solid-State Circuits, IEEE, vol. 30, No. 5, May 1995, pp. 514-521. Sumanen, L. et al., "A 10-bit 200-MS/s CMOS Parallel Piepline A/D Converter," IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 7, Jul. 2001, pp. 1048-1055. Taft, R.C. and Tursi, M.R., "A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8 V Down to 2.2 V," IEEE Journal of Solid-State Circuits