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특허 상세정보

Proportional to temperature voltage generator

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G11C-007/00   
미국특허분류(USC) 365/222; 365/189.09; 327/512; 327/513
출원번호 US-0885897 (2001-06-20)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Christopher P. Maiorana, P.C.
인용정보 피인용 횟수 : 46  인용 특허 : 32
초록

A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in re...

대표
청구항

A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in re...

이 특허에 인용된 특허 (32)

  1. Can Sumer. Bandgap reference voltage circuit with PTAT current source. USP2000016016051.
  2. Imbornone James ; Mourant Jean-Marc. Bandgap start-up circuit. USP2001046222399.
  3. Lucas Charles H. (Fair Oaks CA). CMOS voltage reference circuit. USP1995075434534.
  4. Cha Gi-Won (Kyungki KRX). Circuit for controlling a self-refresh period in a semiconductor memory device. USP1996025495452.
  5. Manning Troy A. (Boise ID). Controlling dynamic memory refresh cycle time. USP1995025392251.
  6. Whatley Roger A. (Austin TX). Delta VBE bias current reference circuit. USP1984054450367.
  7. Paschal Matthew James. Dual current source circuit with temperature coefficients of equal and opposite magnitude. USP2001016181191.
  8. Groe John B.. Dual source for constant and PTAT current. USP1998065774013.
  9. Allen Michael J. (Rescue CA) Baucom Terry L. (Folsom CA). High speed, low power output circuit with temperature compensated noise control. USP1994035291071.
  10. Self Paul W. (Santa Clara CA). High speed, power supply independent CMOS voltage controlled ring oscillator with level shifting circuit. USP1992125175512.
  11. Kirkland Brian ; Meyers Steven ; Williams Bertrand J.. Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture. USP2001016181121.
  12. Suter Richard R. (Beaverton OR). Low voltage VCO temperature compensation. USP1990124978930.
  13. Marvin Dennis F. (Carol Stream IL) Russell Daniel J. (Lake Zurich IL). Method and apparatus for providing a modified temperature compensation signal in a TCXO circuit. USP1995065428319.
  14. Lipp Robert J. (15881 Rose Ave. Los Gatos CA 95030). Monolithic CMOS digital temperature measurement circuit. USP1979084165642.
  15. Nelson Carl T. (San Jose CA). Nonlinearity correction circuit for bandgap reference. USP1986074603291.
  16. Kerry D. Tedrow ; Jeffrey J. Evertt. Oscillator for simultaneously generating multiple clock signals of different frequencies. USP2002036359809.
  17. Lakshmikumar Kadaba R. (Wescosville PA) Nagaraj Krishnaswamy (Somerville NJ) Rich David Arthur (Woodmere NY) Tham Khong-Meng (Reading PA). PTAT current source. USP1997075646518.
  18. Mar Monte F. ; Snyder Warren A.. Programmable oscillator scheme. USP2001026191660.
  19. Atkinson Lee W.. Reducing power consumption in computer memory. USP2000106134167.
  20. Bret Johnson DE; Robert Kaiser DE; Helmut Schneider DE. Refresh drive circuit for a DRAM. USP2002066404690.
  21. Anderson Daryl E. (Corvallis OR). Ring oscillator circuit having improved frequency stability with respect to temperature, supply voltage, and semiconduct. USP1991125072197.
  22. Sakurai Takayasu (Tokyo JPX) Iizuka Tetsuya (Funabashi JPX). Self-refresh control circuit for dynamic semiconductor memory device. USP1987074682306.
  23. Inagaki Yasaburo (Tokyo JPX). Semiconductor memory device with variable self-refresh cycle. USP1987124716551.
  24. Hirano Hiroshige (Nara JPX). Temperature detecting circuit and dynamic random access memory device. USP1994125375093.
  25. Murotani Tatsunori (Tokyo JPX). Temperature responsive refresh control circuit. USP1983074393477.
  26. Kelly Brendan P. (Stockport GB2). Temperature sensing device and a temperature sensing circuit using such a device. USP1995085444219.
  27. Blodgett Greg A.. Temperature sensitive oscillator circuit. USP1999105963103.
  28. Hayashi Isamu (Hyogo JPX) Kondoh Harufusa (Hyogo JPX). Temperature-compensated ring oscillator circuit formed on a semiconductor substrate. USP1993015180995.
  29. Tillinghast Charles W. (Boise ID) Cohen Michael S. (Boise ID) Voshell Thomas W. (Boise ID). Temperature-dependent DRAM refresh circuit. USP1994015278796.
  30. Ewen John F. (Yorktown Heights NY) Soyuer Mehmet (Yorktown Heights NY). VCO bias circuit with low supply and temperature sensitivity. USP1995085440277.
  31. Morgan Donald M.. Voltage and temperature compensated ring oscillator for a memory device. USP1999045898343.
  32. Visocchi Pasqualino,GBX ; Forbes Robert James,CAX. Voltage controlled oscillator power supply and temperature compensation circuit. USP2001036198356.

이 특허를 인용한 특허 피인용횟수: 46

  1. Abugharbieh, Khaldoon S.; Cao, Ying; Richmond, Geoffrey. Bandgap bias circuit compenastion using a current density range and resistive loads. USP2014018638084.
  2. Rana, Vikas; Raj R, Ganesh. CMOS oscillator having stable frequency with process, temperature, and voltage variation. USP2016049325323.
  3. Senriuchi, Tadao; Gokita, Takeo. Circuit and method for temperature detection. USP2009087579899.
  4. Chung, Hoe Ju. Data read circuit for phase change memory device and apparatuses including the same. USP2013018351252.
  5. Umeyama, Takehiko; Ohmi, Kazuyuki. Device for measuring temperature of semiconductor integrated circuit. USP2004086783274.
  6. Klein, Dean A.. Digit line comparison circuits. USP2012108279683.
  7. Klein, Dean A.. Digit line comparison circuits. USP2013058446783.
  8. Shirvani-Mahdavi, Alireza; Chien, George; Chao, Yuan-Ju. Dual reference current generation using a single external reference resistor. USP2010067733076.
  9. Ekkart, Martin; Ettore, Riccio; Moyal, Michael; Schulz, Dirk. High speed sense amplifier. USP2004096798252.
  10. Barth, Roland; Benedix, Alexander; Düregger, Reinhard; Grosse, Stephan. Integrated circuit with temperature sensor and method for heating the circuit. USP2004096798706.
  11. Klein, Dean A.. Low power cost-effective ECC memory system and method. USP2009047526713.
  12. Klein,Dean A.. Low power cost-effective ECC memory system and method. USP2008037340668.
  13. Joo,Yangsung. Low supply voltage temperature compensated reference voltage generator and method. USP2007127313034.
  14. Joo,Yangsung. Low supply voltage temperature compensated reference voltage generator and method. USP2006107116588.
  15. Klein, Dean A.. Memory controller method and system compensating for memory cell data losses. USP2010117836374.
  16. Klein, Dean A.. Memory controller method and system compensating for memory cell data losses. USP2015069064600.
  17. Klein, Dean A.. Memory controller method and system compensating for memory cell data losses. USP2014048689077.
  18. Klein,Dean A.. Memory controller method and system compensating for memory cell data losses. USP2008117447973.
  19. Klein,Dean A.. Memory controller method and system compensating for memory cell data losses. USP2008097428687.
  20. Klein,Dean A.. Memory controller method and system compensating for memory cell data losses. USP2008117447974.
  21. Klein,Dean A.. Memory controller method and system compensating for memory cell data losses. USP2006087099221.
  22. Klein,Dean A.. Memory system and method having selective ECC during low power refresh. USP2008127461320.
  23. Klein, Dean A.; Schreck, John. Memory system and method using ECC to achieve low power refresh. USP2005116965537.
  24. Klein,Dean A.; Schreck,John. Memory system and method using ECC to achieve low power refresh. USP2007027184352.
  25. Pawlowski, J. Thomas; Schreck, John. Memory system and method using ECC with flag bit to identify modified data. USP2013048413007.
  26. Pawlowski, J. Thomas; Schreck, John F.. Memory system and method using ECC with flag bit to identify modified data. USP2013128601341.
  27. Pawlowski, J. Thomas; Schreck, John F.. Memory system and method using ECC with flag bit to identify modified data. USP2014118880974.
  28. Pawlowski, J. Thomas. Memory system and method using partial ECC to achieve low power refresh and fast access to data. USP2013018359517.
  29. Pawlowski, J. Thomas. Memory system and method using partial ECC to achieve low power refresh and fast access to data. USP2016039286161.
  30. Pawlowski, J. Thomas. Memory system and method using partial ECC to achieve low power refresh and fast access to data. USP2014098832522.
  31. Samad, Maheen A.. Method and circuit for generating a constant current source insensitive to process, voltage and temperature variations. USP2004086774666.
  32. Klein, Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2009077558142.
  33. Klein, Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2009117623392.
  34. Klein,Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2007097272066.
  35. Klein,Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2007107277345.
  36. Klein,Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2007107280386.
  37. Klein,Dean A.. Method and system for controlling refresh to avoid memory cell data losses. USP2006107116602.
  38. Uchikoba,Toshitaka; Fujimoto,Tomonori; Ohta,Kiyoto. Semiconductor apparatus capable of performing refresh control. USP2006057038967.
  39. Lim, Jung-Don; Yun, Mi-Kyeong. Temperature adaptive refresh clock generator for refresh operation. USP2005106956397.
  40. Marr, Ken W.. Temperature compensated T-RAM memory device and method. USP2005086934209.
  41. Hong,Yun Seok. Temperature compensated self-refresh circuit. USP2008127471136.
  42. Tesi,Davide. Temperature detector. USP2006057052179.
  43. Pan, Dong. Voltage regulators, amplifiers, memory devices and methods. USP2016049306518.
  44. Pan, Dong. Voltage regulators, amplifiers, memory devices and methods. USP2014058737154.
  45. Pan, Dong. Voltage regulators, amplifiers, memory devices and methods. USP2012088248880.
  46. Kim,Woo Seok; Kim,Ju Hyung. Voltage-controlled oscillators with controlled operating range and related bias circuits and methods. USP2007067233214.