초록 ▼

A process and system for the transfer of information, which is suitable in particular for digital information transfer. At least one information signal is created, consisting of at least one reference component and at least one information component, wherein at least one of these components has a te

A process and system for the transfer of information, which is suitable in particular for digital information transfer. At least one information signal is created, consisting of at least one reference component and at least one information component, wherein at least one of these components has a temporally continuous frequency change during the transfer and, in addition, the reference component and the information component form discrete states for the provision of bit patterns. After receiving, the at least one component with frequency change is transferred into constant intermediate frequencies. From the spectrum of the constant intermediate frequencies, in each case the best-suited signal components are selected, separated as constant frequencies from interference portions and evaluated with regard to the relevant information parameters. This allows a signal transfer with high quality and high transfer rate, even over great distances, for example, under water. Furthermore, a suitable evaluation system is described.

대표청구항 ▼

A process and system for the transfer of information, which is suitable in particular for digital information transfer. At least one information signal is created, consisting of at least one reference component and at least one information component, wherein at least one of these components has a te

A process and system for the transfer of information, which is suitable in particular for digital information transfer. At least one information signal is created, consisting of at least one reference component and at least one information component, wherein at least one of these components has a temporally continuous frequency change during the transfer and, in addition, the reference component and the information component form discrete states for the provision of bit patterns. After receiving, the at least one component with frequency change is transferred into constant intermediate frequencies. From the spectrum of the constant intermediate frequencies, in each case the best-suited signal components are selected, separated as constant frequencies from interference portions and evaluated with regard to the relevant information parameters. This allows a signal transfer with high quality and high transfer rate, even over great distances, for example, under water. Furthermore, a suitable evaluation system is described. exposed at said top surface of said epitaxial layer. 3. A trench DMOS transistor cell as in claim 2 wherein said source region has a portion exposed at said top surface of said epitaxial layer. 4. A trench DMOS transistor cell as in claim 1 wherein depth dtris less than dmaxby an amount sufficient to cause semiconductor surface breakdown to occur at a location closer to said first location than said second location. 5. A trench DMOS transistor cell as in claim 1 wherein said epitaxial layer has a thickness depismall enough to cause semiconductor surface breakdown to occur at a location closer to said first location than said second location. 6. A trench DMOS transistor cell as in claim 1 wherein said trench, when viewed from above said top surface of said epitaxial structure, is polygonal and has a number of sides greater than four. 7. A trench DMOS transistor cell as in claim 6 wherein said number of sides is six. 8. A trench DMOS transistor cell as in claim 1 wherein said trench contains polysilicon isolated from said source and body regions by a layer of gate oxide. 9. A trench DMOS transistor cell as in claim 5 wherein said gate oxide has a thickness sufficient to cause semiconductor breakdown to occur at a location closer to said first location than said second location. 10. A semiconductor wafer comprising a predetermined number of trench DMOS transistor cells in an closed cell configuration, each trench DMOS transistor cell in said semiconductor wafer being a DMOS trench transistor cell as recited in claim 1. 11. A semiconductor wafer comprising a predetermined number of trench DMOS transistor cells in an open cell configuration, each trench DMOS transistor cell in said semiconductor wafer being a DMOS trench transistor cell as recited in claim 1. 12. A trench DMOS transistor cell as in claim 1 wherein said substrate has a dopant concentration higher than said initial dopant concentration of said epitaxial layer, said substrate and said epitaxial layer forming respectively drain and drift regions of said trench DMOS transistor cell. 13. A trench DMOS transistor cell comprising: a substrate of semiconductor material of a first electrical conductivity type having a top surface; a first covering layer of semiconductor material of said first electrical conductivity type, said first covering layer (i) having a dopant concentration less than that of said substrate, (ii) having a top surface and (iii) being contiguous to and overlying the top surface of the substrate; a second covering layer of semiconductor material of a second electrical conductivity type opposite to said first electrical conductivity type having a top surface and being contiguous to the top surface of the first covering layer and extending vertically downward from the top surface of the first covering layer into an upper portion of the first covering layer; a third covering layer of semiconductor material of said first electrical conductivity type having a top surface and being contiguous to and partly overlying the top surface of the second covering layer where the maximum depth of the second covering layer relative to the top surface of the third covering layer is a depth d1; a trench, having side walls and a bottom wall, said side walls extending vertically downward from the top surface of the third covering layer through the third and second covering layers and through a portion of, but not all of, the first covering layer, where the trench has a maximum depth relative to the top surface of the third covering layer equal to a second depth d2less than d1; a layer of oxide positioned within the trench and contiguous to the bottom walls and side walls of the trench so that portions of the trench are filled with the oxide layer; electrically conducting semiconductor material contiguous to the oxide layer and positioned within the trench so that the oxide layer lies between the elect rically conducting semiconductor material and the bottom and side walls of the trench; and three electrodes electrically coupled to the electrically conducting semiconductor material in the trench, to the third covering layer and to the substrate, respectively; wherein junction breakdown occurs away from the trench and into a portion of the second covering layer. 14. A trench DMOS transistor cell as in claim 13 wherein said trench comprises rounded edges of oxidized material. 15. A trench DMOS transistor cell comprising: a substrate; an epitaxial layer above the substrate; a trench in the epitaxial layer, the trench having substantially vertical side walls and having a predetermined depth dtr; and a body region in the epitaxial layer, the body region having a predetermined maximum depth dmax; wherein the depth dtris less than the depth dmax,and wherein junction breakdown occurs away from the trench and into the epitaxial layer. 16. A trench DMOS transistor cell as in claim 15 wherein the substrate is of a first conductivity type, the epitaxial layer is of said first conductivity type and the body region is of a second conductivity type opposite to said first conductivity type. 17. A trench DMOS transistor cell as in claim 16 wherein the epitaxial layer has a top surface and the body region extends from the epitaxial layer's top surface into an upper portion of the epitaxial layer. 18. A trench DMOS transistor cell as in claim 17 wherein a source region is formed in said epitaxial layer. 19. A trench DMOS transistor cell as in claim 18 wherein the source region partially covers the body region. 20. A trench DMOS transistor cell as in claim 19 wherein the body region includes a heavily doped portion extending upward through the epitaxial region and forming a pattern at the epitaxial layer's top surface. 21. A trench DMOS transistor cell as in claim 20 wherein the trench laterally surrounds the pattern of the heavily doped portion of the body region. 22. A trench DMOS transistor cell as in claim 15 further comprising an oxide layer on said trench side walls, said oxide layer having rounded corners along said trench. 23. A trench DMOS transistor cell as in claim 15 further comprising a gate oxide layer within the trench. 24. A trench DMOS transistor cell as in claim 23 further comprising electrically conducting material contiguous to the gate oxide layer, the gate oxide layer being located between the electrically conducting material and the trench. 25. A trench DMOS transistor as in claim 23 further comprising: a first polysilicon layer on a portion of said gate oxide layer; a second oxide layer on a portion of said first polysilicon layer; a second polysilicon layer on a portion of said second oxide layer; and a metal layer wherein said first polysilicon layer extends from the trench to a field region creating an electrical contact to the metal layer and providing continuity from the metal layer to the trench. 26. A trench DMOS transistor cell as in claim 15 wherein a horizontal cross section of the cell has a polygonal shape. 27. A transistor comprising: a first region of a first conductivity type; a second region of a second conductivity type opposite to the first conductivity type overlaying said first region; a third region of said first conductivity type such that said first and third regions are separated by said second region; a trench having substantially vertical side walls and extending through said third and second regions; and a gate in said trench; wherein a portion P of said second region, which portion P is spaced from said trench, extends deeper than said trench so that, if a predetermined voltage is applied to said gate and to said third region and another predetermined voltage is applied to said first region, an avalanche breakdown occurs away from a surface of said trench. 28. A transistor as in claim 27 wherein said portion P of said seco nd region is more heavily doped than another portion of said second region adjacent to said trench. 29. A transistor as in claim 27 wherein said first region comprises a first portion and a second portion over said first portion, said second portion being more lightly doped than said first portion. 30. A transistor as in claim 29 wherein said avalanche breakdown is a reach-through breakdown across said second portion. 31. A transistor as in claim 27 wherein said portion P of said second region extends deeper than said trench by more than 0.5 μm. 32. A transistor as in claim 27 further comprising an insulator between said surface of said trench and said gate. 33. A transistor comprising: a first region of a first conductivity type; a second region of said first conductivity type over said first region, said second region being more lightly doped than said first region; a third region of a second conductivity type opposite to the first conductivity type overlying said second region, said second and third regions forming a junction; a fourth region of said first conductivity type over said third region; a trench having substantially vertical side walls and extending through said fourth and third regions; and a gate in said trench; wherein a deepest part of said third region is laterally spaced from said trench; and wherein a distance between said deepest part of said third region and said first region is less than a depletion width of a planar junction which has the same doping profile as does said junction between said second and third regions at said deepest part of said third region and which is reverse biased around its breakdown voltage. 34. A transistor as in claim 33 wherein the deepest of said third region is doped more heavily than a part of said third region adjacent to said trench. 35. A semiconductor device comprising a semiconductor structure having a trench therein of depth dtrand substantially vertical side walls, said semiconductor structure including a drain region, a source region, a body region, and a gate region within said trench and separated from said body region by a dielectric material, said body region having a maximum depth of dmaxgreater than said depth dtr,wherein junction breakdown occurs away from said trench. 36. A semiconductor device as in claim 35 further comprising a substrate of a first conductivity type and an overlying epitaxial layer of said first conductivity type, wherein said body region is of a second conductivity type opposite to said first conductivity type. 37. A semiconductor device as in claim 36 wherein the epitaxial layer has a top surface and the body region extends from a surface of the epitaxial layer into an upper portion of the epitaxial layer. 38. A semiconductor device as in claim 36 wherein a source region is formed in said epitaxial layer. 39. A semiconductor device as in claim 36 wherein said body region extends upward through the epitaxial layer and forms a pattern at a surface of said epitaxial layer. 40. A semiconductor device as in claim 39 wherein the trench laterally surrounds the pattern of the body region. 41. A semiconductor device as in claim 35 further comprising an oxide layer on said trench walls, said oxide layer having rounded corners along said trench. 42. A semiconductor device as in claim 35 further comprising a gate oxide layer within the trench. 43. A semiconductor device as in claim 42 further comprising electrically conducting material contiguous to said gate oxide layer, wherein said gate oxide layer is located between said electrically conducting material and said trench. 44. A semiconductor device as in claim 42 further comprising: a first polysilicon layer on a portion of said gate oxide layer; a second oxide layer on a portion of said first polysilicon layer; a second polysilicon layer on a portion of said second oxide layer; and a metal layer wherein said first polysilicon layer extends from t