초록 ▼

A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into die

A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i.e., not under probe).

대표청구항 ▼

A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into die

A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i.e., not under probe). ws have a window lens mounted therein constructed of borosilicate glass to block UV below about 320 nm. 7. The UV light according to claim 1 wherein said dichroic cold mirror reflector reflects a high percentage of light in the range of 350 to 450 nm and transmits light in a range longer than 450 nm. 8. The UV light according to claim 1 wherein said dichroic cold mirror reflector reflects a high percentage of in the range of 320 to 380 nm and transmits high percentage of light in a range over 400 nm.