초록 ▼

An uninterruptible transfer switch (UTS) coupled to two or more power sources and a load, said UTS including switches and an inverter, powered through one of several sources routed through rectifiers, capable of sensing power quality of two or more power sources and automatically switching sources w

An uninterruptible transfer switch (UTS) coupled to two or more power sources and a load, said UTS including switches and an inverter, powered through one of several sources routed through rectifiers, capable of sensing power quality of two or more power sources and automatically switching sources when the primary power source is degraded to a predetermined limit and the switching of sources occurring without appreciable power loss on the load side of the UTS.

대표청구항 ▼

An uninterruptible transfer switch (UTS) coupled to two or more power sources and a load, said UTS including switches and an inverter, powered through one of several sources routed through rectifiers, capable of sensing power quality of two or more power sources and automatically switching sources w

An uninterruptible transfer switch (UTS) coupled to two or more power sources and a load, said UTS including switches and an inverter, powered through one of several sources routed through rectifiers, capable of sensing power quality of two or more power sources and automatically switching sources when the primary power source is degraded to a predetermined limit and the switching of sources occurring without appreciable power loss on the load side of the UTS. layer, and wherein the first passivation layer is formed from a vapox over metal layer. 7. The integrated circuit package as recited in claim 1 wherein the second passivation layer is formed from a different material than the first passivation layer. 8. The integrated circuit package as recited in claim 1 wherein the second passivation layer is formed from a resilient coating. 9. The integrated circuit package as recited in claim 8 wherein the second passivation layer is formed from benzocyclobutene. 10. The integrated circuit package as recited in claim 8 wherein the second passivation layer is formed from polyimide. 11. The integrated circuit package as recited in claim 1 wherein the light barrier layer is formed from a non-conductive material. 12. The integrated circuit package as recited in claim 1 wherein the light barrier layer is formed from a conductive material. 13. The integrated circuit package as recited in claim 12 wherein the light shield is electrically floating. 14. The integrated circuit package as recited in claim 12 wherein the light shield is electrically grounded. 15. The integrated circuit package as recited in claim 1 wherein the light shield is formed from Al. 16. The integrated circuit package as recited in claim 1 wherein the integrated circuit package is a flip chip. 17. The integrated circuit package as recited in claim 1 wherein the integrated circuit package is an un-encapsulated integrated circuit package. 18. The integrated circuit package as recited in claim 1 wherein the first passivation layer has a top layer and a bottom layer, the light shield being disposed over the top layer and the bottom layer. 19. The integrated circuit package as recited in claim 18 wherein the top layer is formed from a nitride layer, and wherein the bottom layer is formed from a vapox over metal layer. 20. The integrated circuit package as recited in claim 1 wherein the light shield is formed from Ti. 21. The integrated circuit package as recited in claim 1 wherein the light shield is formed from TiW. 22. The integrated circuit package as recited in claim 1 wherein the light shield is formed from TiN. 23. The integrated circuit package as recited in claim 1 wherein the under bump pad is formed from Al. 24. The integrated circuit package as recited in claim 1 wherein the under bump pad is formed from nickel, nickel-vanadium, copper, chromium or copper-chromium. 25. The integrated circuit package as recited in claim 1 wherein the under bump pad is formed from a different material than the bonding pad. 26. The integrated circuit package as recited in claim 1 wherein the active portions of the integrated circuit include transistors, interconnects, capacitors, or resistors. 27. The integrated circuit package as recited in claim 1 wherein the first passivation layer serves to protect the underlying structures of the integrated circuit and the second passivation layer serves to protect the underlying layers from thermal, chemical, electrical or mechanical stresses associated with attaching the solder bump to the external substrate. 28. An integrated circuit package, comprising: a substrate including a substrate surface having active portions formed thereon, the active portions including light sensitive areas; a bonding pad disposed over the substrate surface; a light shield disposed over a portion of the bonding pad and over a portion of the substrate surface that includes at least the light sensitive areas of the active portions, the light shield being opaque to ambient light; a first passivation layer disposed between the light shield and the substrate surface and between the light shield and the portion of the bonding pad; and a second passivation layer disposed over the light shield, wherein the second passivation layer is formed from a different material than the first passivation layer. 29. The integrated circuit package as recited in claim 28 wherein the first passivation layer serves to protect the underl