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A wireless communications system including at least one base station operative to communicate with terminals on a plurality of carrier frequencies in repetitive time slots defined thereon is operated by assigning an entire time slot or a spreading-code defined subchannel of a time slot to a terminal

A wireless communications system including at least one base station operative to communicate with terminals on a plurality of carrier frequencies in repetitive time slots defined thereon is operated by assigning an entire time slot or a spreading-code defined subchannel of a time slot to a terminal based on a communications constraint associated with the terminal. The communications constraint may include a performance requirement, such as an information rate or an error rate, and a signal reception condition, such as signal to noise ratio. According to another aspect, a wireless communications system determines a communications constraint associated with a terminal. The system assigns a time slot, a spreading code, a coding rate and a bandwidth to the terminal based on the determined communications constraint. Preferably, the system assigns a time slot, a spreading code, a coding rate and a bandwidth to the terminal such that at least one of an available bandwidth, a number of available time slots, and a number of available spreading codes is optimized. Related apparatus are also described.

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A wireless communications system including at least one base station operative to communicate with terminals on a plurality of carrier frequencies in repetitive time slots defined thereon is operated by assigning an entire time slot or a spreading-code defined subchannel of a time slot to a terminal

A wireless communications system including at least one base station operative to communicate with terminals on a plurality of carrier frequencies in repetitive time slots defined thereon is operated by assigning an entire time slot or a spreading-code defined subchannel of a time slot to a terminal based on a communications constraint associated with the terminal. The communications constraint may include a performance requirement, such as an information rate or an error rate, and a signal reception condition, such as signal to noise ratio. According to another aspect, a wireless communications system determines a communications constraint associated with a terminal. The system assigns a time slot, a spreading code, a coding rate and a bandwidth to the terminal based on the determined communications constraint. Preferably, the system assigns a time slot, a spreading code, a coding rate and a bandwidth to the terminal such that at least one of an available bandwidth, a number of available time slots, and a number of available spreading codes is optimized. Related apparatus are also described. connector, to the second module and the first, second, third, and fourth chips on the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module and the first, second, third, and fourth chips on the first module. 3. The system of claim 2, wherein the first clock signal path continues from the first, second, third, and fourth chips of the second module to the second module connector, the circuit board and to at least one termination. 4. The system of claim 3, wherein the at least one termination is on a controller which also supplies the first clock signal. 5. The system of claim 2, wherein the second clock signal path continues from the first, second, third, and fourth chips of the first module to the first module connector, the circuit board and to at least one termination. 6. The system of claim 1, wherein impedances of the clock paths in the modules are at least 50% higher than the clock paths on the circuit boards. 7. A system comprising: first and second modules; a circuit board including first and second module connectors to receive the first and second modules, respectively; a first data path of conductors to provide data signals to and receive data signals from first and second chips on the first module and third and fourth chips on the second module; a second data path of conductors to provide data signals to and receive data signals from third and fourth chips on the first module and first and second chips on the second module; a first clock path of conductors to carry a first clock signal to the first, second, third, and fourth chips on the first module and then to the first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module. 8. The system of claim 7, wherein writing on the first data path occurs synchronously with respect to the first clock signal and reading on the first data path occurs synchronously with respect to the second clock signal. 9. The system of claim 7, wherein writing on the second data path occurs synchronously with respect to the second clock signal and reading on the second data path occurs synchronously with respect to the first clock signal. 10. The system of claim 7, wherein: writing on the first data path occurs synchronously with respect to the first clock signal and reading on the first data path occurs synchronously with respect to the second clock signal; and writing on the second data path occurs synchronously with respect to the second clock signal and reading on the second data path occurs synchronously with respect to the first clock signal. 11. The system of claim 7, wherein the first clock signal path continues from the first, second, third, and fourth chips of the second module to the second module connector, the circuit board and to at least one termination. 12. The system of claim 11, wherein the at least one termination is on a controller which also supplies the first clock signal. 13. The system of claim 7, wherein the second clock signal path continues from the first, second, third, and fourth chips of the first module to the first module connector, the circuit board and to at least one termination. 14. The system of claim 13, wherein the at least one termination is on a controller which also supplies the first clock signal. 15. The system of claim 7, wherein the first and second data paths each include uni-directional conductors and some of the uni-direction conductors provide the data signals to the chips and some of the uni-directional conductors receive data signals from the chips. 16. The system of claim 7, wherein the first and second data paths each include bi-directional conductors. 17. A system comprising: first and second modules; a circuit board including first and sec ond module connectors to receive the first and second modules, respectively; a first data path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to a first group of terminations; a second data path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to a second group of terminations; a first clock path of conductors to carry a first clock signal and extending from the circuit board to the first module connector, to the first module and first, second, third, and fourth chips on the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module and first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal and extending from the circuit board to the second module connector, to the second module and the first, second, third, and fourth chips on the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module and the first, second, third, and fourth chips on the first module. 18. The system of claim 17, wherein writing on the first data path occurs synchronously with respect to the first clock signal and reading on the first data path occurs synchronously with respect to the second clock signal. 19. The system of claim 17, wherein writing on the second data path occurs synchronously with respect to the second clock signal and reading on the second data path occurs synchronously with respect to the first clock signal. 20. The system of claim 17, wherein: writing on the first data path occurs synchronously with respect to the first clock signal and reading on the first data path occurs synchronously with respect to the second clock signal; and writing on the second data path occurs synchronously with respect to the second clock signal and reading on the second data path occurs synchronously with respect to the first clock signal. 21. The system of claim 17, wherein the first clock signal path continues from the first, second, third, and fourth chips of the second module to the second module connector, the circuit board and to at least one termination. 22. The system of claim 17, wherein the at least one termination is on a controller which also supplies the first clock signal. 23. The system of claim 17, wherein the second clock signal path continues from the first, second, third, and fourth chips of the first module to the first module connector, the circuit board and to at least one termination. 24. The system of claim 17, wherein the at least one termination is on a controller which also supplies the first clock signal. 25. The system of claim 17, wherein impedances of the first and second clock signal paths match that of corresponding data paths. 26. A system comprising: a circuit board including a first module connector having first, second, and third clock signal connector connections and a second module connector having first, second, and third clock signal connector connections; a first clock path of conductors including sections extending from the circuit board to the first clock signal connector connection of the first module connector, from the second clock signal connector connection of the first module connector to the third clock signal connector connection of the second module connector; and a second clock path of conductors including sections extending from the circuit board to the first clock signal connector connection of the second module connector, from the second clock signal connector connection of the second module connector to the third clock signal connector connection of the first module connector. 27. The system of claim 26, wherein the section from the second clock signal connector connection of the first module connector to the third clock signal connector connection of the second module connector includes the circuit board. 28. The system of claim 26, further comprising additional clock signal connector connections. 29. The system of claim 26, further comprising: a first data path of conductors including sections coupled to a first group of data signal connector connections on the first module connector and a second group of data signal connector connections on the second module connector; and a second data path of conductors including sections coupled to a second group of data signal connector connections on the first module connector and a first group of data signal connector connections on the second module connector.