A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to defin
A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
대표청구항▼
A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to defin
A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate. de layer on said first and second doped polysilicon regions; forming photoresist shapes on said third silicon oxide layer, and on said first and second silicon shapes; performing an anisotropic dry etching procedure by using photoresist shapes as masks to remove portions of said third silicon oxide layer to form overlying silicon oxide shapes, removing portions of said first and second doped polysilicon regions to form a first polysilicon source shape of a first conductivity type in said first region and a second polysilicon source shape of a second conductivity type in said second region of said semiconductor substrate; removing portions of said second silicon oxide layer to form underlying silicon oxide spacers; removing said photoresist shapes; performing a wet etch procedure to remove said thin silicon nitride layer and said silicon nitride shape, to expose a portion of said first silicon shape, to be used as a first channel region in said first region of semiconductor substrate, and to remove said thin silicon nitride layer to expose a portion of said second silicon shape, to be used as a second channel region in said second region of said semiconductor substrate, wherein said first channel region having a larger channel length than said second channel region; growing a silicon dioxide gate insulator layer on said first channel region and on said second channel region, while forming a fourth silicon oxide layer on exposed sides of said first and second polysilicon source shapes; depositing a thick, second intrinsic polysilicon layer on said first silicon oxide layer; performing ion implantation procedures to convert a first portion of said thick, second intrinsic polysilicon layer to a first doped thick polysilicon region of a first conductivity type, and to convert a second portion of said thick, second intrinsic polysilicon layer to a second doped thick polysilicon region of a second conductivity type; and performing an anisotropic dry etch procedure by using said silicon oxide shapes as a hard mask to remove portions of said first and second doped thick polysilicon regions, thereby forming a first self-aligned polysilicon gate structure in said first region of said semiconductor substrate, and forming a second self-aligned polysilicon gate structure in said second region of said semiconductor substrate. 2. The method of claim 1, wherein said first type CMOS devices are N channel or NMOS devices, while said second type CMOS devices are P channel or PMOS devices. 3. The method of claim 1, wherein said first heavily doped drain region is a heavily doped N type drain region, obtained via implantation of arsenic or phosphorous ions, at an energy between about 40 to 90 KeV, and at a dose between about 1E15 to 8E15 atoms/cm2. 4. The method of claim 1, wherein said second heavily doped drain region is a heavily doped P type drain region, obtained via implantation of boron ions, at an energy between about 2 to 10 KeV, and at a dose between about 1E15 to 6E15 atoms/cm2. 5. The method of claim 1, wherein said first silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 200 Angstroms. 6. The method of claim 1, wherein said silicon nitride shape is defined via anisotropic RIE procedures, using Cl2as an etchant, performed to a silicon nitride layer which in turn is obtained via LPCVD or PECVD procedures at a thickness between about 300 to 5000 Angstroms. 7. The method of claim 1, wherein said thin silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 50 to 500 Angstroms. 8. The method of claim 1, wherein said first channel opening, and said second channel opening, are formed via an anisotropic RIE procedure using CHF3as an etchant for said first and second silicon oxide, oxide and using Cl2as an etchant for said thin silicon nitride layer and said silicon nitride shape. 9. The method of cl
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Hubler Graham K. (Alexandria VA) Donovan Edward P. (Annandale VA) Van Vechten Deborah (Baltimore MD), Method for producing substoichiometric silicon nitride of preselected proportions.
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Dolins Steven B. (Dallas TX) Srivastava Aditya (Richardson TX) Flinchbaugh Bruce E. (Dallas TX) Gunturi Sarma S. (Richardson TX) Lassiter Thomas W. (Garland TX) Love Robert L. (McKinney TX), Process and apparatus for detecting aberrations in production process operations.
Bruel Michel (Veurey FRX) du Port de Poncharra Jean (St. Martin-Le-Vinoux FRX), Process for producing an insulating layer buried in a semiconductor substrate by ion implantation.
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Kramler, Josef; Kuhn-Kuhnenfeld, Franz; Gerber, Hans-Adolf, Process for the manufacture of semiconductor wafers with a rear side having a gettering action.
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Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
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Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
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Takayama, Toru; Maruyama, Junya; Yamazaki, Shunpei, Method of peeling thin film device and method of manufacturing semiconductor device using peeled thin film device.
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