초록 ▼

The present invention is a method for acknowledgment of receipt of a message in a network, where the network includes a plurality of nodes. The method includes sending a message from a first node of the plurality of nodes destined for a second node of the plurality of nodes; setting a timer for the

The present invention is a method for acknowledgment of receipt of a message in a network, where the network includes a plurality of nodes. The method includes sending a message from a first node of the plurality of nodes destined for a second node of the plurality of nodes; setting a timer for the first node for receipt of an acknowledgment packet from the second node; determining if a wait acknowledge packet is received by the first node; and resetting the timer if the wait acknowledge packet is received by the first node. The present invention adds a wait acknowledge event to the state in the acknowledgment protocol which waits for an acknowledgement packet from the destination node. The wait acknowledge packet notifies the recipient that the message sent by the originating node has been received and forwarded. As long as the message is being properly forwarded to the next hop, wait acknowledge packets will continue to be sent to the originating node. In this manner, the amount of time the originating node waits for the acknowledgment packet from the destination node is dynamic and is dependent upon the actual length of time it takes for the message to be transmitted through the network. This method reduces waste of network resources and minimizes the problem of unintentional duplicate messages.

대표청구항 ▼

The present invention is a method for acknowledgment of receipt of a message in a network, where the network includes a plurality of nodes. The method includes sending a message from a first node of the plurality of nodes destined for a second node of the plurality of nodes; setting a timer for the

The present invention is a method for acknowledgment of receipt of a message in a network, where the network includes a plurality of nodes. The method includes sending a message from a first node of the plurality of nodes destined for a second node of the plurality of nodes; setting a timer for the first node for receipt of an acknowledgment packet from the second node; determining if a wait acknowledge packet is received by the first node; and resetting the timer if the wait acknowledge packet is received by the first node. The present invention adds a wait acknowledge event to the state in the acknowledgment protocol which waits for an acknowledgement packet from the destination node. The wait acknowledge packet notifies the recipient that the message sent by the originating node has been received and forwarded. As long as the message is being properly forwarded to the next hop, wait acknowledge packets will continue to be sent to the originating node. In this manner, the amount of time the originating node waits for the acknowledgment packet from the destination node is dynamic and is dependent upon the actual length of time it takes for the message to be transmitted through the network. This method reduces waste of network resources and minimizes the problem of unintentional duplicate messages. ommunication channel signals to be combined are signals transmitted in a CDMA telecommunications system. 7. Device for combining, in a plurality of cycles, a plurality of digital communication channels, each being transmitted via communication lines having a first bit width, comprising a cascade arrangement of a plurality of apparatuses, each including: a multiplexer for multiplexing the plurality of digital communication channels into a multiplexed digital signal, a first register for storing intermediate results, an adder for adding samples of the digital communication channels and intermediate results stored in the first register, wherein one of the inputs of the adder is connected to the multiplexer via a first connection line having the first bit width, the output of the adder is connected to the input of the first register via a second connection line having a second bit width larger than the first bit width, and the output of the first register is connected to the other input of the adder via a third connection line having the second bit width, wherein, in a number of cycles corresponding to the number of digital communication channels, one combined output sample is generated by successively adding in each one cycle one sample of one of the communication channels to a previously obtained intermediate result stored in the first register, and wherein the output bit width of an apparatus of a particular stage of the cascade arrangement is determined by .right brkt-top.lg2(ni(2wi-1)) with ni=number of input signals of the apparatus of a particular stage, wi=bit width of input signals. 8. Apparatus according to claim 3, wherein the second bit width is an integer equal or smaller than the first limit and equal or larger than the second limit.