Control arrangement and method for electronic device
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/00
출원번호
US-0036659
(2001-12-21)
발명자
/ 주소
Atanus, Ronald D.
Mears, Gregory C.
Mikosz, Richard P.
O'Leary, Raymond P.
Ennis, Michael G.
Ruta, Joseph W.
출원인 / 주소
S&C Electric Co.
대리인 / 주소
Lapacek, James V.
인용정보
피인용 횟수 :
1인용 특허 :
15
초록▼
A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is chan
A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is changed by the receipt of a momentary signal to change the conducting state of the electronic switch. For example, according to one specific arrangement, the momentary signal is a secure, complex signal such that appropriate decoding and detection of the proper signal is required to change the conducting state of the electronic switch.
대표청구항▼
A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is chan
A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is changed by the receipt of a momentary signal to change the conducting state of the electronic switch. For example, according to one specific arrangement, the momentary signal is a secure, complex signal such that appropriate decoding and detection of the proper signal is required to change the conducting state of the electronic switch. , for determining a difference between the input signal and the reference signal, and for generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference. 7. The improved differential integrator of claim 4, wherein the nap mode circuit comprises: logic circuitry for receiving the nap signal and the feedback signal and for determining the sleep mode based thereon; and storage circuitry, coupled to the logic circuitry, for storing the differential charge by disconnecting a differential path during the sleep mode; wherein a differential voltage is held constant prior to a wake-up mode to shorten a wake-up time. 8. The improved differential integrator of claim 1, further comprising: a level shifter circuit, coupled to the integrating gain boosted cascode circuit, for level shifting the output signal so as to generate a level shifted output signal. 9. The improved differential integrator of claim 8, wherein the level shifter circuit comprises: first charge storage circuitry for receiving differential signals at an input node; charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals; second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon; and at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween. 10. The improved differential integrator of claim 1, wherein the integrating gain boosted cascode circuit is a first integrating gain boosted cascode circuit, further comprising: a second integrating gain boosted cascode circuit, coupled to an output node of the first integrating gain boosted cascode circuit, for generating a pair of output signals. 11. The improved differential integrator of claim 1, wherein the integrating gain boosted cascode circuit comprises: a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation; and a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage. 12. An integrating gain boosted cascode circuit comprising: a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation; and a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage. 13. The integrating gain boosted cascode circuit of claim 12, further comprising: a cascode structure, coupled to an output node of the gain boosted cascode structure, for increasing output resistance of the gain boosted cascode structure. 14. The integrating gain boosted cascode circuit of claim 12, further comprising: a cascode structure, coupled to an output node of the gain boosted cascode structure, for providing a feedback path from the cascode structure to the gain boosted cascode structure. 15. The integrating gain boosted cascode circuit of claim 12, further comprising: a current source, coupled to an input node of the gain boosted cascode structure, for providing current to the gain boosted cascode structure.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (15)
Cook Wayne Kenneth ; Windholz Philip James, AC transfer switch.
Bonneau Victor B. (Yellow Springs OH) Kuzkin Gary M. (Oakwood OH) Wagoner Robert G. (Troy OH) Overman John A. (Huber Heights OH), Aerospace power control system for monitoring and reliably transferring power buses.
O'Leary Raymond P. ; Ennis Michael G. ; Ruta Joseph W. ; Segredo Anthony F., Control arrangement and method for high-speed source-transfer switching system.
Mikosz, Richard P.; Atanus, Ronald D.; Ennis, Michael G.; Mears, Gregory C.; O'Leary, Raymond P.; Ruta, Joseph W., Control arrangement and method for power electronic system.
Lagree James L. (Robinson Township PA) Hanna James R. (Brighton Township PA) McGill James W. (Singapore SGX), Method and apparatus for transferring between electrical power sources which adaptively blocks transfer until load volta.
Ichikawa Kosaku,JPX ; Hirata Akio,JPX ; Kawakami Kazuto,JPX ; Satoh Kazuhiro,JPX, Power converter with voltage drive switching device monitored by device parameters and electric parameters.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.